Intel Sees Challenges In Keeping Up With Moore's Law
Although Intel will manage to advance Moore's Law for the foreseeable future, keeping up with it is becoming more challenging as chip geometries shrink.
Moore's Law is based on a theory that the number of transistors that can be placed on silicon doubles every two years, which brings more features on chips and provides speed boosts.
During a speech at the Jeffries Global Technology, Media, and Telecom Conference this week, William Holt, executive vice president and general manager of Intel's Technology Manufacturing Group, admitted that as chips get smaller, maintaining pace with Moore's Law is perhaps more difficult today than it was in years past.
"Are we closer to an end than we were five years ago? Of course. But are we to the point where we can realistically predict that end, we don't think so. We are confident that we are going to continue to provide the basic building blocks that allow improvements in electronic devices," Holt said.
However, Holt says Moore's Law isn't dead.
"I'm not here to tell you that I know what's going to happen 10 years from now. This is much too complicated a space. At least for the next few generations we are confident we don't see the end coming," Holt said, talking about generations of manufacturing processes.
Holt said that manufacturing smaller chips with more features becomes a challenge as chips could be more sensitive to a "wider class of defects." The sensitivities and minor variations increase, and a lot of attention to detail is required.
"As we make things smaller, the effort that it takes to make them actually work is increasingly difficult," Holt said. "There are just more steps and each one of those steps needs additional effort to optimize."
Intel is expected to start shipping Atom chips made using the 22-nm process later this year, followed up by chips made using the 14-nm process next year.
Earlier this week, Intel said upcoming 22-nanometer Atom chips based on a new architecture called Silvermont will be up to three times faster and five times more power-efficient than predecessors made using the older 32-nm process. The Atom chips include Bay Trail, which will be used in tablets later this year; Avoton for servers; and Merrifield, due next year, for smartphones. Intel is trying to catch up with ARM, whose processors are used in most smartphones and tablets today.
The process of scaling down chip sizes will require lots of ideas, many of which are taking shape in university research being funded by chip makers and semiconductor industry associations, Holt said. Some of the ideas revolve around new transistor structures and also materials to replace traditional silicon.
"Strain is one example that we did in the past, but using germanium instead of silicon is certainly a possibility that is being researched. Even more exotically, going to III-V material provide advantages," Holt said. "And then there are new devices that are being evaluated as well as different forms of integration."
The family of III-V materials includes gallium arsenide.
The next big move for chip manufacturers is to 450-mm wafers, which will allow more chips to be made in factories at less cost. Intel in July last year invested $2.1 billion in tools maker ASML to enable smaller chip circuits and larger wafers. TSMC and Samsung also invested in ASML. Intel's investment in ASML was also tied to the development of tools for implementation of EUV (extreme ultraviolet) technology, which enables more transistors to be crammed on silicon.
Holt could not predict when Intel would move to 450-millimeter wafers, and hoped it would come by the end of the decade. EUV has proved challenging, he said, adding that there are engineering problems to work through before it is implemented.
Nevertheless, Holt was confident about Intel's ability to scale down and to remain ahead of rivals like TSMC and GlobalFoundries, which are trying to catch up on manufacturing with the implementation of 3D transistors in their 16-nm and 14-nm processes, respectively, next year. But Intel is advancing to the second generation of 3D transistors and unlike its rivals, also shrinking the transistor, which the company hopes would give it a manufacturing advantage.
During a speech at the Jeffries Global Technology, Media, and Telecom Conference this week, William Holt, executive vice president and general manager of Intel's Technology Manufacturing Group, admitted that as chips get smaller, maintaining pace with Moore's Law is perhaps more difficult today than it was in years past.
"Are we closer to an end than we were five years ago? Of course. But are we to the point where we can realistically predict that end, we don't think so. We are confident that we are going to continue to provide the basic building blocks that allow improvements in electronic devices," Holt said.
However, Holt says Moore's Law isn't dead.
"I'm not here to tell you that I know what's going to happen 10 years from now. This is much too complicated a space. At least for the next few generations we are confident we don't see the end coming," Holt said, talking about generations of manufacturing processes.
Holt said that manufacturing smaller chips with more features becomes a challenge as chips could be more sensitive to a "wider class of defects." The sensitivities and minor variations increase, and a lot of attention to detail is required.
"As we make things smaller, the effort that it takes to make them actually work is increasingly difficult," Holt said. "There are just more steps and each one of those steps needs additional effort to optimize."
Intel is expected to start shipping Atom chips made using the 22-nm process later this year, followed up by chips made using the 14-nm process next year.
Earlier this week, Intel said upcoming 22-nanometer Atom chips based on a new architecture called Silvermont will be up to three times faster and five times more power-efficient than predecessors made using the older 32-nm process. The Atom chips include Bay Trail, which will be used in tablets later this year; Avoton for servers; and Merrifield, due next year, for smartphones. Intel is trying to catch up with ARM, whose processors are used in most smartphones and tablets today.
The process of scaling down chip sizes will require lots of ideas, many of which are taking shape in university research being funded by chip makers and semiconductor industry associations, Holt said. Some of the ideas revolve around new transistor structures and also materials to replace traditional silicon.
"Strain is one example that we did in the past, but using germanium instead of silicon is certainly a possibility that is being researched. Even more exotically, going to III-V material provide advantages," Holt said. "And then there are new devices that are being evaluated as well as different forms of integration."
The family of III-V materials includes gallium arsenide.
The next big move for chip manufacturers is to 450-mm wafers, which will allow more chips to be made in factories at less cost. Intel in July last year invested $2.1 billion in tools maker ASML to enable smaller chip circuits and larger wafers. TSMC and Samsung also invested in ASML. Intel's investment in ASML was also tied to the development of tools for implementation of EUV (extreme ultraviolet) technology, which enables more transistors to be crammed on silicon.
Holt could not predict when Intel would move to 450-millimeter wafers, and hoped it would come by the end of the decade. EUV has proved challenging, he said, adding that there are engineering problems to work through before it is implemented.
Nevertheless, Holt was confident about Intel's ability to scale down and to remain ahead of rivals like TSMC and GlobalFoundries, which are trying to catch up on manufacturing with the implementation of 3D transistors in their 16-nm and 14-nm processes, respectively, next year. But Intel is advancing to the second generation of 3D transistors and unlike its rivals, also shrinking the transistor, which the company hopes would give it a manufacturing advantage.
