JEDEC Announces Key Attributes of Upcoming DDR4 Standard
JEDEC Solid State Technology Association today announced selected
key attributes of its DDR4 (Double Data Rate 4) standard.
With publication forecasted for mid-2012, JEDEC DDR4 will represent
a significant advancement in performance with reduced power usage as
compared to previous generation technologies.
DDR4 is being developed with a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. Its speed, voltage and architecture are all being defined with the goal of simplifying migration and facilitating adoption of the standard.
A DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. Understanding that enhancements in technology will occur over time, DDR4 will help protect against technology obsolescence by keeping the I/O voltage stable.
The per-pin data rates, over time, will be 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its expected peak of 1.6 GT/s, it is likely that higher performance levels will be proposed for DDR4 in the future. Other performance features planned for inclusion in the standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667 Mhz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes.
The DDR4 architecture is an 8n prefetch with bank groups, including the use of two or four selectable bank groups. This will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each of the unique bank groups. This concept will improve overall memory efficiency and bandwidth, especially when small memory granularities are used. Additional features in development include:
- Three data width offerings: x4, x8 and x16
- New JEDEC POD12 interface standard for DDR4 (1.2V)
- Differential signaling for the clock and strobes
- New termination scheme versus prior DDR versions: In DDR4, the DQ bus shifts termination to VDDQ, which should remain stable even if the VDD voltage is reduced over time.
- Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin
- Burst length of 8 and burst chop of 4
- Data masking
- DBI: to help reduce power consumption and improve data signal integrity, this feature informs the DRAM as to whether the true or inverted data should be stored
- New CRC for data bus: Enabling error detection capability for data transfers - especially beneficial during write operations and in non-ECC memory applications.
- New CA parity for command/address bus: Providing a low-cost method of verifying the integrity of command and address transfers over a link, for all operations.
- DLL off mode supported
To facilitate comprehension and adoption of the DDR4 standard, JEDEC is planning to host a DDR4 Technical Workshop following the publication of the standard.
Joe Macri, Chairman of JEDEC?s JC-42.3 Subcommittee for DRAM Memories, said "Numerous memory device, system, component and module producers are collaborating to finalize the DDR4 standard, which will enable next generation systems to achieve greater performance with lower power consumption."
JEDEC's next committee meeting will be held in Chicago in September, 2011.
DDR4 is being developed with a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. Its speed, voltage and architecture are all being defined with the goal of simplifying migration and facilitating adoption of the standard.
A DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. Understanding that enhancements in technology will occur over time, DDR4 will help protect against technology obsolescence by keeping the I/O voltage stable.
The per-pin data rates, over time, will be 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its expected peak of 1.6 GT/s, it is likely that higher performance levels will be proposed for DDR4 in the future. Other performance features planned for inclusion in the standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667 Mhz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes.
The DDR4 architecture is an 8n prefetch with bank groups, including the use of two or four selectable bank groups. This will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each of the unique bank groups. This concept will improve overall memory efficiency and bandwidth, especially when small memory granularities are used. Additional features in development include:
- Three data width offerings: x4, x8 and x16
- New JEDEC POD12 interface standard for DDR4 (1.2V)
- Differential signaling for the clock and strobes
- New termination scheme versus prior DDR versions: In DDR4, the DQ bus shifts termination to VDDQ, which should remain stable even if the VDD voltage is reduced over time.
- Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin
- Burst length of 8 and burst chop of 4
- Data masking
- DBI: to help reduce power consumption and improve data signal integrity, this feature informs the DRAM as to whether the true or inverted data should be stored
- New CRC for data bus: Enabling error detection capability for data transfers - especially beneficial during write operations and in non-ECC memory applications.
- New CA parity for command/address bus: Providing a low-cost method of verifying the integrity of command and address transfers over a link, for all operations.
- DLL off mode supported
To facilitate comprehension and adoption of the DDR4 standard, JEDEC is planning to host a DDR4 Technical Workshop following the publication of the standard.
Joe Macri, Chairman of JEDEC?s JC-42.3 Subcommittee for DRAM Memories, said "Numerous memory device, system, component and module producers are collaborating to finalize the DDR4 standard, which will enable next generation systems to achieve greater performance with lower power consumption."
JEDEC's next committee meeting will be held in Chicago in September, 2011.
