Rambus today announced functional silicon of a double data rate (DDR) server DIMM (dual inline memory module) buffer chipset prototype for the next generation DDR5 memory technology.
DDR5 data buffers (DB) and DDR5 registering clock drivers (RCD), are targeted for use in DDR5 Registered DIMMs (RDIMMs) and DDR5 Load Reduced DIMMs (LRDIMMs), to deliver higher bandwidth, performance and capacity versus unbuffered DIMMs. RDIMMS and LRDIMMs reduce load on the CPU and improve the signal integrity of the command/address bus. Specifically, the DDR5 DB will reduce the effective load on the data bus, which enables higher-capacity DRAMs on the module without reducing latency.
The silicon-proven memory buffer chip prototype is capable of achieving the speeds required for the upcoming DDR5 standard, Rambus claims.
The JEDEC standards group plans to release before June the DDR5 spec as the default memory interface for next-generation servers. According to JEDEC, DDR5 memory will support data rates up to 6.4 Gbits/second delivering 51.2 GBytes/s max, up from 3.2 Gbits and 25.6 GBytes/s for today's DDR4. The new version will push the 64-bit link down to 1.1V and burst lengths to 16 bits from 1.2V and 8 bits. In addition, DDR5 lets voltage regulators ride on the memory card rather than the motherboard. With that, server DIMM chipsets, like registered clock drivers and data buffers, will be critical to enabling higher memory capacities while maintaining peak performance.
The DDR5 standard will arrive about the same time Jedec releases its NVMDIMM-p interface for memory modules supporting a mix of DRAM and persistent memory. Intel plans to roll out server DIMMs next year using its 3D XPoint chips. Others are expected to ship NVMDIMM-p cards using 3D NAND.
Rambus says that the server DIMM chip prototype leverages the company's signal integrity and low power, mixed-signal design expertise to enable development of next-generation solutions for future data center workloads.
However, some analysts note it comes at a time of emerging alternatives in persistent memories, new computer architectures and chip stacks.
DDR5 remains power hungry so the server industry may still need to come up with persistent memory alternatives.
Process technology shrinks for DRAMs are approaching the physical limits of its core capacitors, leading some to project the end the memory designs in five to ten years. Higher error rates are already requiring correcting code circuitry on the chips.
Graphics processors from AMD and Nvidia have already moved to High Bandwidth Memory chip stacks to boost speed and density. However, Rambus claims that chip stacks are still an expensive approach limited to high-end GPUs, FPGAs and communications ASICs.