Renesas has introduced the industry's first lineup of PCIe 6.0-compliant clock buffers and multiplexers. The new devices will enable companies to create motherboards and other devices that should meet PCIe 6.0 performance and signal integrity requirements while also being compatible with PCIe 5.0 applications.

Renesas is introducing 11 new RC190xx clock buffers and four new RC192xx multiplexers with additive jitter of only 4fs RMS, making them virtually noiseless, a feature critical for PCIe Gen6 applications. The new clock buffers also have a 1.4 ns in-out delay, a 35ps out-of-out skew, and a -80dB power supply rejection ratio (PSRR) at 100kHz. The new chips complement Renesas' low-jitter 9SQ440, 9FGV1002, and 9FGV1006 clock generators, allowing the company to provide a full PCIe 6.0 timing solution.

Consumer graphics cards and solid-state drives are unlikely to require 256 GBps bi-directional bandwidth over a 16-lane interface or 64 GBps bi-directional bandwidth over a 4-lane interface any time soon. However, in a data center, bandwidth is everything. Meanwhile, designing and testing ultra-complex PCIe Gen 6 circuits will take time, so the sooner hardware developers begin developing new products, the better. Developers of next-generation server platforms may be able to begin designing motherboards, accelerators, network cards, and SSDs as a result of this.

"By delivering the first discrete timing solution for PCIe Gen 6, Renesas is enabling customers to develop the next-generation of high-performance systems," said Rich Wawrzyniak, principal analyst for Semico Research in a statement from Renesas. "It will be interesting to see the innovative implementations that result from this new capability, especially when considering how solutions for the emerging chiplet market are starting to evolve, with the need for increasing speed and bandwidth as an underlying constant."

The PCIe Gen 6 specification raises the data transfer rate to 64 GTps and uses pulse amplitude modulation with four levels (PAM-4) of signaling as well as forward error correction to increase the total bandwidth of a 16-lane PCIe slot to 256 GBps in both directions (FEC). A very high data transfer rate and a new signal encoding method necessitate not only new logical enhancements to the specification (e.g., FEC enhanced with CRC), but also increased requirements for clock signal quality — clock jitter performance of a PCIe Gen 6 subsystem should be less than 100fs RMS. This is where the brand-new clock buffers (also known as clock drivers) and multiplexers enter the picture.

The operation of a circuit must be synchronized, but due to different path lengths between two clock paths, or because of gated or rippled clocks, the same-sourced clock signal may arrive at different registers at different times. This is known as clock skew or timing skew, and it can cause hold time violations. Clock buffers enable synchronous and efficient clock distribution by preserving the clock properties of the input signal, and minimizing additive jitter noise is especially important for PCIe 6.0 subsystems.

A multiplexer is essentially a switch with multiple inputs and a single output that is used for signal distribution. Because we're dealing with a 64 GTps data transfer rate, MUXes must handle this signal rate while also ensuring clean signals, which is why brand-new PCIe Gen 6 multiplexers are required.

"PCIe Gen6 timing will be at the heart of new equipment in data centers, high-speed networking, and other applications," explained Zaher Baidas, Vice President of Renesas' Timing Products Division. "Renesas is providing customers with the first timing solution to enable these new, higher-performance systems, as we have done for previous generations. Our customers know that we have the technical expertise and market knowledge to ensure that their products can meet future demands."