In triple patterning, patterns of the circuit are drawn on the wafer before cutting, and this is done three times for precision on existing equipment, which is crucial for designing chips to be smaller. Triple-patterning allows bi-directional routing.
First devices to use the 10nm chips should appear early next year with a follow-on 10LPP process ramping late next year, it added. The new Glaxy S8 smartphone, which is expected to be unveiled in February, wil be powerd by 10nm SoCs, designed by Qualcomm and Samsung (Snapdragon 830 and Exynos), and manufactured by Samsung's foundry.
Shanghai-based SMIC is on pace to grow revenues 29% this year while Samsung is only expected to grow about 4% from 2015, according to IC Insights. SMIC’s growth is in trailing edge planar technologies; it is still in development with a 16nm FinFET process.
Samsung is the last of the big foundries to give details on its plans at 10nm. TSMC and Intel announced -- in September and in August respectively -- they are ramping 10nm processes that will be in production next year. Globalfoundries announced in September will skip the 10nm node which it said does not push triple-patterning lithography to its limits, driving to a 7nm process it aims to have in production in late 2018.
Intel said its 10nm process will have sport a 54nm gate pitch, packing transistors more densely than any competitors. Foundries use of names such as 10nm no longer points to any specific metric, so mileage is expected to vary considerably between companies.
TSMC suggested its 10nm node will be fairly short lived compared to its 7nm process which could have limited availability in 2017. TSMC’s 10nm node is aimed to win the business of making the A-series SoCs in Apple’s iPhone 8.
Last week, TSMC said it started developing the 3-nano process. The world's largest semiconductor foundry enterprise recently became the sole provider of APs for Apple's iPhone 7 and the larger 7 Plus.