TSMC Announces Move to 20nm Process
Taiwan Semiconductor Manufacturing Company, Ltd. announced today at its 2010 Technology Symposium that it will skip the 22nm manufacturing process node and move directly to a 20nm technology.
After the 28-nm node, it plans to skip the 22-nm ''full node'' and will move directly to the 20-nm ''half node.''
During his address to nearly 1,500 TSMC customers and third party alliances, Dr. Shang-yi Chiang, TSMC Senior Vice President, Research & Development, said that the move to 20nm creates a superior gate density and chip performance to cost ratio than a 22nm process technology and makes it a more viable platform for advanced technology designers. He also announced that TSMC is expected to enter 20nm risk production in the second half of 2012. TSMC will also not offer an 18-nm process.
The technology will be based on a planar process with enhanced high-K metal gate, novel strained silicon, and low-resistance copper Ultra-Low-K interconnects, TSMC said. Dr. Chiang also indicated that the company has demonstrated record-setting feasibility of other transistor structures such as FinFET and high-mobility devices.
The technical rationale behind the move is based on the capability of patterning technology and layout design methodologies required at these advanced technology nodes.
"We have reached a point in advanced technology development where we need to be actively concerned about the ROI of advanced technology. We also need to broaden our thinking beyond the process technology barriers that are inherent in every new node," Dr. Chiang pointed out. "Collaborative and co-optimized innovation is required to overcome the technological and economic challenges."
Unlike its previous processes in recent times--which focused on low power first--TSMC's initial 20-nm process will be a high-performance technology. Following that process, it will roll out a low-power technology.
With the announcement, TSMC is seeking to gain an edge over its leading-edge rivals, such a GlobalFoundries, Samsung and UMC.Recently, GlobalFoundries Inc. said it is starting work on its 22-nm CMOS process, which is due out in the second half of 2012. Intel is expected to be at the 22-nm node by the fourth quarter of 2011.
TSMC is currently shipping its 40-nm process. The company's next step is to release the first 28 LP (low-power) chips at the end of June this year, Chiang said in a presentation last November.
"The first high-k metal gate we call 28 HP for the high performance application will be introduce the end of September this year, and followed by three months later December will be the 28 HPL. This is the first high-k metal gate introduction for the low power application," he said.
During his address to nearly 1,500 TSMC customers and third party alliances, Dr. Shang-yi Chiang, TSMC Senior Vice President, Research & Development, said that the move to 20nm creates a superior gate density and chip performance to cost ratio than a 22nm process technology and makes it a more viable platform for advanced technology designers. He also announced that TSMC is expected to enter 20nm risk production in the second half of 2012. TSMC will also not offer an 18-nm process.
The technology will be based on a planar process with enhanced high-K metal gate, novel strained silicon, and low-resistance copper Ultra-Low-K interconnects, TSMC said. Dr. Chiang also indicated that the company has demonstrated record-setting feasibility of other transistor structures such as FinFET and high-mobility devices.
The technical rationale behind the move is based on the capability of patterning technology and layout design methodologies required at these advanced technology nodes.
"We have reached a point in advanced technology development where we need to be actively concerned about the ROI of advanced technology. We also need to broaden our thinking beyond the process technology barriers that are inherent in every new node," Dr. Chiang pointed out. "Collaborative and co-optimized innovation is required to overcome the technological and economic challenges."
Unlike its previous processes in recent times--which focused on low power first--TSMC's initial 20-nm process will be a high-performance technology. Following that process, it will roll out a low-power technology.
With the announcement, TSMC is seeking to gain an edge over its leading-edge rivals, such a GlobalFoundries, Samsung and UMC.Recently, GlobalFoundries Inc. said it is starting work on its 22-nm CMOS process, which is due out in the second half of 2012. Intel is expected to be at the 22-nm node by the fourth quarter of 2011.
TSMC is currently shipping its 40-nm process. The company's next step is to release the first 28 LP (low-power) chips at the end of June this year, Chiang said in a presentation last November.
"The first high-k metal gate we call 28 HP for the high performance application will be introduce the end of September this year, and followed by three months later December will be the 28 HPL. This is the first high-k metal gate introduction for the low power application," he said.
