New Package Technology Realizes Miniaturization at the Bare Chip Level
Renesas Electronics today announced the successful development of a new ultra-compact microchip package technology for use in microcontroller unit (MCU) products.
The newly developed technology is a kind of IC packaging technology that employs wafer-level redistribution technology, called the FO-WLP (Fan-Out Wafer-Level Package) technology, which makes it ideal for ultra-compact MCU products. It utilizes multilayer interconnect technology and chip bonding technology, two elemental technologies from Renesas Electronics' SMAFTI (SMArt chip connection with Feed-Through Interposer) technology for 3-D IC. (In contrast to an integrated circuit chip in which elements are arranged in a two-dimensional (planar) configuration, three-dimensional integrated circuit (3-D IC) technology uses stacked layer configuration with high-density interlayer connection such as microbumps and through-silicon vias (TSV) to achieve improved performance, reduced power consumption, and higher-level integration.)
The FO-WLP production process consists of (1) formation of redistribution layer (RDL) with copper pillar bumps (CPB) on a support wafer, (2) high-speed chip-to-wafer bonding technology using chips with electroless plated pads, (3) high-productive wafer-level mold underfilling technology for approximately 10-micrometer (΅m) gaps.
Using FO-WLP, Renesas Electronics has succeeded in packaging an 8-bit MCU with a chip size of 1.6 millimeters (mm) Χ 1.6 mm in a package measuring only 2.0 mm Χ 2.0 mm Χ 0.3 mm, a reduction in volume of 80 percent from the previous package size of 3.0 mm Χ 3.0 mm Χ 0.7 mm. The two-layer metal interconnects consist of polyimide and copper (Cu), the minimum wire width/space is 15 ΅m/10 ΅m, and the interlayer via size is 20 ΅m.
Test results of the chip-RDL-board electrical connections show excellent reliability in a typical condition of 1,000 −40/+125 C temperature cycles, the company said.
The newly developed FO-WLP technology can be used in a new SiWLP (System in Wafer-Level Package) that enables multiple chips, such as an MCU and an analog/RF IC chip, to be arranged side by side with high-density interconnections between them. It makes possible greater miniaturization and higher integration, allowing multiple chips to be contained in a SiWLP about the same size as a single chip.
Interest is focusing on more efficient use of energy through smart grids as well as environmental sensing and control technologies such as sensor networks. At the same time, sensing and feedback technologies used in patient monitoring systems and the like are becoming increasingly important in fields such as healthcare. SiWLP technology not only makes it possible to produce ultra-compact modules integrating MCUs and analog devices, it also enhances affinity with the environment by combining sensors, actuators, and communication functions needed to implement an interface with the environment or the human body.
Renesas Electronics views the SiWLP technology as a cornerstone in support of advancement of these fields and plans to continue promoting R&D and product development moving forward.
Renesas Electronics announced the results of this research at the Electronics System Integration Technology Conference (ESTC 2010) held September 14-16 in Berlin, Germany.
Sample shipments of MCU products utilizing FO-WLP are scheduled to begin in December 2011.
The FO-WLP production process consists of (1) formation of redistribution layer (RDL) with copper pillar bumps (CPB) on a support wafer, (2) high-speed chip-to-wafer bonding technology using chips with electroless plated pads, (3) high-productive wafer-level mold underfilling technology for approximately 10-micrometer (΅m) gaps.
Using FO-WLP, Renesas Electronics has succeeded in packaging an 8-bit MCU with a chip size of 1.6 millimeters (mm) Χ 1.6 mm in a package measuring only 2.0 mm Χ 2.0 mm Χ 0.3 mm, a reduction in volume of 80 percent from the previous package size of 3.0 mm Χ 3.0 mm Χ 0.7 mm. The two-layer metal interconnects consist of polyimide and copper (Cu), the minimum wire width/space is 15 ΅m/10 ΅m, and the interlayer via size is 20 ΅m.
Test results of the chip-RDL-board electrical connections show excellent reliability in a typical condition of 1,000 −40/+125 C temperature cycles, the company said.
The newly developed FO-WLP technology can be used in a new SiWLP (System in Wafer-Level Package) that enables multiple chips, such as an MCU and an analog/RF IC chip, to be arranged side by side with high-density interconnections between them. It makes possible greater miniaturization and higher integration, allowing multiple chips to be contained in a SiWLP about the same size as a single chip.
Interest is focusing on more efficient use of energy through smart grids as well as environmental sensing and control technologies such as sensor networks. At the same time, sensing and feedback technologies used in patient monitoring systems and the like are becoming increasingly important in fields such as healthcare. SiWLP technology not only makes it possible to produce ultra-compact modules integrating MCUs and analog devices, it also enhances affinity with the environment by combining sensors, actuators, and communication functions needed to implement an interface with the environment or the human body.
Renesas Electronics views the SiWLP technology as a cornerstone in support of advancement of these fields and plans to continue promoting R&D and product development moving forward.
Renesas Electronics announced the results of this research at the Electronics System Integration Technology Conference (ESTC 2010) held September 14-16 in Berlin, Germany.
Sample shipments of MCU products utilizing FO-WLP are scheduled to begin in December 2011.
