TSMC Introduces Its 16nm FinFET Technology
Taiwan Semiconductor Manufacturing Co Ltd talked about its 16nm new process technology at the International Electron Devices Meeting (IEDM) 2013, which took place from Dec 9 to 11, 2013, in Washington, D.C..
Designed for systems on a chip for mobile and computing devices, the 16nm technology will be used by TSMC by the end of 2013.
It is the firt time that TSMC employs a three-dimensional transistor (FinFET) for its 16nm process. The company said that the technology enables an 100% increasment in the density of transistors, comapred to its 28nm process technology (high-k gate dielectric film/metal gate). More transistors per square unit allowed for a 35% faster operation speed as well as a 55% lower consumption.
TSMC provided some technical details of its 16nm technology.
The company "shared" some technology from its current 20nm and the 28mn processes, such as BEOL (back end of line) metal interconnection technology and the gate-last (replacement gate) method that had been used for the 28nm process technology. But this time, the BEOL metal interconnection technology uses FinFETs in place of planar transistors.
TSMC also employed seven-layer Cu-low-k interconnection. Double-patterning and pitch-splitting techniques are used for the patterning of the first metal interconnection and the formation of fins, respectively.
TSMC has already applied the 16nm process technology in the deleopment of a 128-Mbit SRAM prototype. The company said that the chip can be produced with a high yield rate.
It is the firt time that TSMC employs a three-dimensional transistor (FinFET) for its 16nm process. The company said that the technology enables an 100% increasment in the density of transistors, comapred to its 28nm process technology (high-k gate dielectric film/metal gate). More transistors per square unit allowed for a 35% faster operation speed as well as a 55% lower consumption.
TSMC provided some technical details of its 16nm technology.
The company "shared" some technology from its current 20nm and the 28mn processes, such as BEOL (back end of line) metal interconnection technology and the gate-last (replacement gate) method that had been used for the 28nm process technology. But this time, the BEOL metal interconnection technology uses FinFETs in place of planar transistors.
16nm |
Technology features |
Process |
FinFET, HKMG, Dual-Oxide, Cu/LK |
Digital |
Core & I/O, multi-Vt |
Analog |
High-R, Varator, BJT, FMOM |
Memory |
6T (HD,HC, HP), 2P-8T, DP SRAM, ROM |
Chip ID/ repair |
Electrical fuse |
LC-Tank |
Inductor, RF-Varactor, RF-MOM |
De-Cap |
HD-MiM, MOSCAP |
ESD |
Gated-diode, STI-diode, Snapback MOS |
TSMC also employed seven-layer Cu-low-k interconnection. Double-patterning and pitch-splitting techniques are used for the patterning of the first metal interconnection and the formation of fins, respectively.
TSMC has already applied the 16nm process technology in the deleopment of a 128-Mbit SRAM prototype. The company said that the chip can be produced with a high yield rate.
