ARM today made available a power-optimized dual-core hard macro implementation of the ARM Cortex-A15 processor. The ARM Cortex-A15 implementation provides power efficiency and is capable of delivering up to 10,000 DMIPS within a constrained mobile power envelope.

The ARM Cortex-A15 hard macro development is the result of the synergy arising from the combination of ARM Cortex processor IP, Artisan physical IP, CoreLink systems IP and ARM's integration capabilities, and utilizes TSMC?s 28nm HPM process. The complete low leakage implementation features integrated NEON SIMD technology and a virtual floating point engine, and includes a 1MB level 2 cache to deliver a balance of performance and power. It has been designed to power a wide range of power-sensitive handheld devices such as mobile phones and tablets. The Cortex-A15 implementation could also be used by designers of big.LITTLE processing systems as it can be paired with a dual- or quad-core Cortex-A7 processor.

This dual-core hard macro was implemented using ARM Artisan 9-track libraries and incorporates ARM POP Technology for the Cortex-A15 on TSMC?s 28nm HPM process.