TechInsights has explored SK Hynix's U-shaped NAND cell architecture and compares it with the 3D NAND approaches followded by Micron, Toshiba, Intel and Samsung.

SK Hynix has been developing several types of 3D NAND cell structures, including DC-SF (three-dimensional Dual Control-gate with Surrounding Floating-gate, 2010) and SMArT (Stacked Memory Array Transistor with ONO layer, 2012).

TechInsights took a look at SK Hynix's 3D version 2 with H28U74301AMR UFS package markings, found in the LG V20 smartphone. They found that four NAND die are in a 64 GB package, which means each 3D NAND die has 128 Gb, likely using multi-level cell (MLC) rather than triple-level cell (TLC). Currently, other major 3D NAND players - such as Samsung, Toshiba, SanDisk, Micron, and Intel - have their 3D NAND products with TLC.

The chip's die area is measured at 88.36 mm2, which means that the memory density is 1.45 Gb/mm2 on a die with 67.5% memory array efficiency. The memory density on the die is quite low compared to other players' 3D NAND TLC products, such as the Micron 32L 3D NAND (2.28 Gb/mm2), Toshiba/SanDisk 48L 3D NAND (2.43 Gb/mm2), and Samsung 48L V-NAND (2.57 Gb/mm2) because the SK Hynix H27DGS8 die used for UFS products might be an MLC die instead of a TLC die.

Referring to memory density on a plane (or a tile for Micron's 3D NAND die), SK Hynix 3D NAND (ver. 2) die has 2.15 Gb/mm2, which is still lower than Micron?s 32L (2.63 Gb/mm2), Toshiba/SanDisk's 48L (3.45 Gb/mm2), and Samsung?s 48L (3.56 Gb/mm2).

TechInsights also compared the memory density and memory array efficiency from major 3D NAND manufacturers. The memory array efficiency (84.9%) of Micron/Intel?s 3D NAND is higher than others because of their array on CMOS circuits in which the CMOS decoders and sense-amps are sitting under the 3D FG-NAND memory array. The memory efficiency of SK Hynix 3D NAND (67.5%) is a little lower than Samsung?s (70.0%) and Toshiba/SanDisk?s (69.9%).