Elpida Ships Fully-Buffered DIMM Samples for Advanced Performance in Next-Generation Servers
Elpida Memory, Inc., Japan's leading global supplier of Dynamic Random Access Memory (DRAM), today announced that it has shipped samples of its Fully-Buffered Dual in-line Memory Modules (FB-DIMM) that provide advanced performance for next-generation servers.
The industry standard specification is complete and will be confirmed by JEDEC (Joint Electron Device Engineering Counsel). FB-DIMMs have been designed to provide significant performance gains over current Registered DIMM solutions, and they will offer unprecedented speeds up to 4.8 Gigabits per second (Gbps) data rate, equivalent to 6.4 Gigabytes per second (GB/s) data bandwidth. Existing DDR2 Registered DIMMs offer only 3.2 Gigabytes per second.
"Next-generation servers require significant performance boosts that cannot be achieved with current Registered DIMM solutions," said Jun Kitano, director of Technical Marketing for Elpida Memory (USA). "The emergence of the FB-DIMM, with its ability to increase the number DIMMs per channel while maintaining high-speed operation, will help to eliminate memory bottlenecks that limit overall server performance. Elpida's FB-DIMM is an initial step toward enabling improved memory technology for future server platforms."
FB-DIMMs vs. Registered DIMMs
Elpida's FB-DIMM utilizes JEDEC-standard DDR2 SDRAM. However, the module design is completely new. In the new FB-DIMM, all signals - clock, address, command and data - to and from the DRAM on the module are buffered at the high-speed Advanced Memory Buffer (AMB) chip located on the DIMM. This helps to secure the DRAM timing margins during high-speed operation with a much shorter signal path between the DRAM and the AMB.
The FB-DIMM also adopts a Point-to-Point connection on the bus between the memory controller and the DIMM, as well as between the DIMMs themselves. This allows increased bus speed with a shorter connection path. It also greatly improves the maximum number of DIMMs that can be loaded on the bus - up to eight 2-rank DIMMs - with less concern about signal degradation.
By comparison, existing standard Registered DIMMs have a stub-bus architecture along the memory bus between each DIMM and the memory controller. As the memory frequency increases, the controller must reduce the number of DIMMs loaded on the memory bus to secure the signal quality and the timing margin along the lengthy signal path between the DRAM devices on the module and the controller on the motherboard. Therefore, Registered DIMMs that provide 3.2 GB/s bandwidth (PC2-3200 / DDR2-400) are limited to four 1-rank DIMMs, or two 2-rank DIMMs. This limitation has presented a bottleneck in achieving improved performance in server applications where both high-speed and high-capacity are essential.
As processor speeds continue to increase, and as the server architecture changes, FB-DIMMs will be required to support next-generation server platforms.
"Next-generation servers require significant performance boosts that cannot be achieved with current Registered DIMM solutions," said Jun Kitano, director of Technical Marketing for Elpida Memory (USA). "The emergence of the FB-DIMM, with its ability to increase the number DIMMs per channel while maintaining high-speed operation, will help to eliminate memory bottlenecks that limit overall server performance. Elpida's FB-DIMM is an initial step toward enabling improved memory technology for future server platforms."
FB-DIMMs vs. Registered DIMMs
Elpida's FB-DIMM utilizes JEDEC-standard DDR2 SDRAM. However, the module design is completely new. In the new FB-DIMM, all signals - clock, address, command and data - to and from the DRAM on the module are buffered at the high-speed Advanced Memory Buffer (AMB) chip located on the DIMM. This helps to secure the DRAM timing margins during high-speed operation with a much shorter signal path between the DRAM and the AMB.
The FB-DIMM also adopts a Point-to-Point connection on the bus between the memory controller and the DIMM, as well as between the DIMMs themselves. This allows increased bus speed with a shorter connection path. It also greatly improves the maximum number of DIMMs that can be loaded on the bus - up to eight 2-rank DIMMs - with less concern about signal degradation.
By comparison, existing standard Registered DIMMs have a stub-bus architecture along the memory bus between each DIMM and the memory controller. As the memory frequency increases, the controller must reduce the number of DIMMs loaded on the memory bus to secure the signal quality and the timing margin along the lengthy signal path between the DRAM devices on the module and the controller on the motherboard. Therefore, Registered DIMMs that provide 3.2 GB/s bandwidth (PC2-3200 / DDR2-400) are limited to four 1-rank DIMMs, or two 2-rank DIMMs. This limitation has presented a bottleneck in achieving improved performance in server applications where both high-speed and high-capacity are essential.
As processor speeds continue to increase, and as the server architecture changes, FB-DIMMs will be required to support next-generation server platforms.
