Hynix Semiconductor has developed a 185MHz 512Megabit mobile DDR SDRAM with ECC (Error Correction Code). The built in ECC, similar to that used in NAND Flash, ensures data integrity while reducing current consumption by almost 50%, according to the company.

At 185MHz clock speed, a throughput of up to 1.5Gbytes of data per second can be attained with a 32-bit I/O. The ECC feature in this product allows for the extension of the refresh interval which in turn significantly reduces power consumption. Additionally, the 512Mb ECC Mobile DDR offers the traditional low power features necessary for a wide range of mobile applications. These features include reduced power supply voltage, temperature compensated self refresh (TCSR), partial array self refresh (PASR), and deep power down (DPD) modes.



Hynix's 512Mb ECC mobile DDR is manufactured on the Company's 80nm process technology and is offered in JEDEC standard pin-out and packages.

Hynix plans to assemble the 512Mb ECC mobile DDR with NAND flash and offer a multi-chip package (MCP) or a package-on-package (POP) stack.

Mass production of the products is slated to begin at the second half of 2007, with samples scheduled for early third quarter.