"This is very much a strong statement of IBM's pursuit of the low-power marketplace and, specifically, going after the very high growth in consumer electronics," Richard Busch, director of IBM ASIC products, said. "This is an expansion of our thrust in that direction with a very targeted offering."
The low-power 65nm ASIC offering, Cu-65LP, has leakage currents reduced by as much as 30 times from the previous 90nm ASIC offering, IBM said, adding that performance is increased as much as 20 percent over the previous 90nm ASIC offering.
Both of the 65nm ASICs being detailed today at the 2005 Design Automation Conference -- the low-power Cu-65LP and the high-performance Cu-65HP -- have the ability to pack nearly twice as many circuits on a die compared with the equivalent 90nm offering.
The chips are built using strained silicon and statistical techniques in timing and optimization to address process variation. The ASICs also provide power management features that include voltage Island technique to control power, a multiple threshold voltage library, and integrated noise, power and timing methodology to allow first pass success designs.
The offering includes standard-cell logic design libraries; multiple I/O families; embedded SRAM and DRAM; a collection of cores, including industry leading high-speed SerDes and embedded microprocessors highlighting PowerPC architecture; as well as a wide range of packaging solutions.
The low-power ASIC offering is built on top of ARM/Artisan libraries and coupled with ASIC methodology. ARM is co-developing these 65nm low-power libraries and selected cores with IBM, the company said, withholding further details on the agreement.
The Cu-65LP design kit will be available this quarter, followed by the high-performance design kit later in the year. Volume production for the Cu-65 low power and high performance offerings will begin in Q1 and Q3 of 2007, respectively.