The extreme ultraviolet (EUV) lithography at 5nm nodes introduces random defects that could cloud chip roadmaps, but patterning experts from the Imec research institute in Belgium claim that there are techniques to eliminate them.

The top chip makers - Globalfoundries, Samsung and TSMC - are racing to make their EUV systems run efficiently, using 250W light sources for 7nm production next year. But still, they will have to deal with defects, which increase the costs and complexity of making advanced semiconductors.

The latest defects are cropping up at critical dimensions around 15nm needed to make 5nm chips for foundry processes targeting 2020. EUV maker ASML is preparing a next-generation EUV system for printing finer features, but those systems won't be available until about 2024.

The random defects could be imperfectly made holes, tears in lines or shorts where two lines or two holes meet. Given their extremely small size, spotting them is very hard.

Dutch ASML's latest EUV scanners can print the 20nm and larger critical dimensions that foundries plan at 7nm, said Greg McIntyre, a patterning expert from the Imec research institute in Belgium. However, their ability to make finer lines and holes is unclear, he said at this week's 2018 SPIE Advanced Lithography Conference SPIE annual conference for lithographers in San Fransciso.

Imec continues to advance the readiness of EUV lithography with particular focus on EUV single exposure of Logic N5 metal layers, and of aggressive dense hole arrays. Imec's approach to enable EUV single patterning at these dimensions is based on the co-optimization of various lithography enablers, including materials, metrology, design rules, post processing and a fundamental understanding of critical EUV processes.

With the industry making improvements in EUV infrastructure readiness, first insertion of EUV lithography in high-volume manufacturing is expected in the critical back-end-of-line metal and via layers of the foundry N7 Logic technology node, with metal pitches in the range of 36-40nm.

Imec's research focuses on the next node (32nm pitch and below), where various patterning approaches are being considered. These approaches vary considerably in terms of complexity, wafer cost, and time to yield, and include variations of EUV multipatterning, hybrid EUV and immersion multipatterning, and EUV single expose.

Imec's path comprises a co-optimization of various lithography enablers, including resist materials, stack and post processing, metrology, computational litho and design-technology co-optimization, and a fundamental understanding of EUV resist reaction mechanisms and of stochastic effects. Based on this approach, imec has demonstrated promising advances including initial electrical results, on EUV single exposure focusing on two primary use cases: logic N5 32nm pitch metal-2 layer and 36nm pitch contact hole arrays.

Working with its many materials partners, imec assessed different resist materials strategies, including chemically amplified resists, metal-containing resists and sensitizer-based resists. Particular attention was paid to the resist roughness, and to nano-failures such as nanobridges, broken lines or missing contacts that are induced by the stochastic EUV patterning regime. These stochastic failures are currently limiting the minimum dimensions for single expose EUV. Based on this work, imec delved into the fundemental understanding of stochastics and identified the primary dependencies influencing failures. Additionally, various metrology techniques and hybrid strategies have been employed to ensure an accurate picture of the reality of stochastics.

As resist materials advances alone will likely be inssufient to meet the requirements, imec has also focused on co-optimizing the photomask, film stack, EUV exposures and etch towards an integrated patterning flow to achieve full patterning of the structures. This was done using computational lithography techniques such as optical proximity correction and source mask optimization, complemented by design-technology co-optimization to reduce standard library cell areas. Finally, etch-based post-processing techniques aimed at smoothing the images after the lithography steps yields encouraging results for dense features.

"Co-optimization of these multiple knobs is key to achieving optimized patterning and edge placement error control," according to McIntyre.

However, not everyone shares McIntyre's optimism. While lithographers will be able to create 5nm and even 3nm devices by using two and three passes with an EUV stepper, a rising tide of chip defects ultimately will drive engineers to new, fault-tolerant processor architectures such as neural networks, said retired Intel lithographer Yan Borovodsky.

While yield losses seem to be inevitable, George Gomba, a vice president of research at Globalfoundries, called for productivity and availability improvements, since the current NXE 3400 systems are "not meeting some road map conditions we desire, so there is still some uncertainty at 7nm". He also called for more work on so-called actinic systems - still in development - that inspect EUV masks before lithographers cover them with protective pellicles.

Another factor that may be contributing to the 5nm defects is a lack of homogeneity in the current EUV resist materials.