Marvell Launches New OCTEON TX2 Family of Multi-Core Infrastructure Processors
Marvell has announced its fifth generation of Octeon processors, the Octeon TX2 family, aiming at expanding its further into the telecom infrastructure processor market.
The new infrastructure processors are targeting a wide variety of wired and wireless networking equipment including switches, routers, secure gateways, firewall, network monitoring, 5G base stations, and smart network interface controllers (NICs).
Marvell’s OCTEON TX2 infrastructure processor family combines up to 36 cores, based on the Arm v8-A architecture with configurable and programmable hardware accelerator blocks, connected by Marvell’s coherent interconnect. Compared to architectures that process data solely on CPU cores, these accelerator blocks – which include security, packet processing, and traffic management functions – are able to meet demanding performance and power requirements. The integrated hardware accelerators offer 2.5x improvement over Marvell’s previous generation of OCTEON processors with scalable throughput ranging from 10Gbps to over 200 Gbps.
The OCTEON platform is enabled by an SDK. The platform includes firmware, Linux OS and multiple distributions, virtualization, containers, data plane development kit (DPDK), protocol stacks, infrastructure management and orchestration like OpenStack and Kubernetes, and virtual network functions (VNFs). In addition, Marvell supports a full routing stack including TCP, SSL, and IPSEC support and DPDK support for L2/L3 forwarding and IPSEC.
Marvell’s CN91xx, CN92xx, CN96xx, and CN98xx processor families include:
- 4 - 36 cores based on the Armv8-A architecture ranging up to 2.4 GHz frequency
- Rich I/O with 25G SerDes-based I/O interfaces, e.g. 100GbE, 50GbE, 40GbE, 25GbE, 10GbE, 2.5GbE, 1GbE Ethernet ports and PCIe gen4 interfaces supporting root-complex and end-point configurations
- Enhanced NITROX V security co-processors which accelerate a set of asymmetric and symmetric cryptographic operations
- Hardware accelerators support with comprehensive packet processing hardware offload, including packet receive, flexible packet parsing, flow classification, buffer management, QoS (quality of service), transmit processing and hierarchical traffic shaping and scheduling
- Load-balancing and work scheduling hardware which accounts for QoS, packet ordering and synchronization
Marvell’s OCTEON TX2 CN9130, CN92xx and CN96xx are available now with reference designs and development kits. Marvell’s CN98xx will begin sampling in the second quarter of 2020.
The company also introduced a line of processors, the Fusion family, that is based on the TX2 platform and aimed directly at 5G base stations.