Marvell today introduced a dual 400GbE (Gigabit Ethernet) PHY transceiver with 100GbE serial electrical I/O capabilities, designed to drive high-density optical infrastructure.

Marvell’s new PHY device with 100G serial I/Os enables the doubling of faceplate bandwidth on datacenter networks while reducing the total power consumption and cost per bit. The new device offers 256-bit MACsec encryption to ensure point-to-point security, Class C compliant precision time protocol (PTP) timestamping for synchronization and Marvell’s 112G PAM4 SerDes technology for high-density 400GbE and 100GbE deployments.

The advent of 100G serial electrical signaling optical modules will allow 1:1 mapping between electrical and optical I/O speeds. This removes the additional circuitry inside 400GbE optical modules to convert from 50G electrical I/Os to 100G per lambda optical I/Os, reducing cost and power. The new PHY transceivers provide networking OEMs with the technology required for high-density dual 400G/octal 100G optical modules in QSFP-DD and OSFP form factors for cloud and data center applications.

Marvell’s newest dual 400GbE MACsec PHY, the 88X9121P, enables interfacing between the current generation of switch ASICs with the next generation of optics and vice versa by supporting translation between 50G PAM4 and 100G PAM4 based implementations of 400GbE, 200GbE and 100GbE.

The 88X9121P is the latest addition to Marvell’s Alaska C Ethernet transceiver family. It is fully compliant with IEEE standards for 400GbE, 100GbE and 50GbE, and exceeds the electrical specifications to interface with QSFP-DD and OSFP optical modules.

The Marvell 88X9121P is currently sampling.