NEC Develops New Design Method for High Speed LSI with More than 50 Million Transistors
NEC announced that they have succeeded in the development of a new design method for large-scale integrations (LSIs) with more than 50 million transistors, operating at a speed of several hundred megahertz.
NEC and NEC Electronics' new design method introduces a "Border Moving Method" into the
design process, which eliminates the need for the budgeting process and re-designing of
hierarchical blocks, shortening the total length of time required for backend design for
large scale and high speed LSI to 1/3 of the conventional design method.
With large scale LSI design, all of the LSIs are usually not designed simultaneously (flat design) as it is difficult for designers to grasp the complete picture and there is a high probability that the design will exceed the limitations of available tools. It is therefore common to deploy the "hierarchical design method." With this method, an LSI is divided into several hierarchical blocks. The blocks are designed independently and are later assembled into one LSI. Each block is small enough to be handled by a designer and available tools. In addition, the divided blocks can be concurrently designed by several designers, making this method extremely effective for implementing large scale LSIs in short time frames.
However, there are some downfalls to this method. In particular, "Budgeting (timing constraint budgeting)" is an inevitable bottleneck in the hierarchical design method. Budgeting is carried out in order to impose a timing constraint on a signal path between two hierarchical blocks. However, the constraint cannot be considered for the entire path, it can only be considered for the three partial signal paths separately: 1) the signal path inside one hierarchical block, 2) the signal path between two hierarchical blocks and 3) the signal path inside another hierarchical block. In other words, each of the three partial paths must fulfill its own timing constraint and the entire signal path must satisfy the original constraint at the same time. It is only after the design of the blocks is completed that the designers can tell whether the timing constraint for the signal path between the blocks can be satisfied. If the constraint cannot be satisfied, the designers must repeatedly assign a different timing constraint to the blocks and design them all over again from scratch, until the entire signal path fulfills its timing constraint. Thus, budgeting is a very difficult and time-consuming process even for one signal path. Typical large scale and high speed LSIs have several tens of thousands of signal paths connecting hierarchical blocks. Budgeting of a large number of signal paths takes several months and lengthens the total LSI design period.
NEC and NEC Electronics' new design method introduces a "Border Moving Method." After designing hierarchical blocks, the method modifies the boundary of blocks and moves partial signal paths out of the blocks. These partial signal paths, which used to reside inside the blocks, and the partial signal path connecting the blocks are then combined into one signal path. As a result, only the delay for the single signal path has to be considered, eliminating the need for budgeting and re-designing hierarchical blocks. This breakthrough research result has been achieved through the introduction of an intelligent algorithm that minimizes the modification of the boundary, and which has been elaborated enough to allow practical application in the design of real large-scale LSI.
This new method has already been applied to the actual design of several LSIs with satisfactory results. Moreover, the trial proved a substantial performance improvement and a decrease in design time as compared with conventional design methods. NEC and NEC Electronics consider this method to be effective in shortening the design period for large scale and high speed LSIs, and are ready to apply the technology in-house to LSIs for NEC's products such as supercomputers (SX Series), enterprise server products (NX 7700i Series) and platforms, allowing the timely provision of high quality products to customers.
NEC presented the results of this research on the 27th of July at the Design Automation Conference 2006 (DAC 2006), the world's largest international conference on system LSI design (July 23-28, San Francisco, USA).
With large scale LSI design, all of the LSIs are usually not designed simultaneously (flat design) as it is difficult for designers to grasp the complete picture and there is a high probability that the design will exceed the limitations of available tools. It is therefore common to deploy the "hierarchical design method." With this method, an LSI is divided into several hierarchical blocks. The blocks are designed independently and are later assembled into one LSI. Each block is small enough to be handled by a designer and available tools. In addition, the divided blocks can be concurrently designed by several designers, making this method extremely effective for implementing large scale LSIs in short time frames.
However, there are some downfalls to this method. In particular, "Budgeting (timing constraint budgeting)" is an inevitable bottleneck in the hierarchical design method. Budgeting is carried out in order to impose a timing constraint on a signal path between two hierarchical blocks. However, the constraint cannot be considered for the entire path, it can only be considered for the three partial signal paths separately: 1) the signal path inside one hierarchical block, 2) the signal path between two hierarchical blocks and 3) the signal path inside another hierarchical block. In other words, each of the three partial paths must fulfill its own timing constraint and the entire signal path must satisfy the original constraint at the same time. It is only after the design of the blocks is completed that the designers can tell whether the timing constraint for the signal path between the blocks can be satisfied. If the constraint cannot be satisfied, the designers must repeatedly assign a different timing constraint to the blocks and design them all over again from scratch, until the entire signal path fulfills its timing constraint. Thus, budgeting is a very difficult and time-consuming process even for one signal path. Typical large scale and high speed LSIs have several tens of thousands of signal paths connecting hierarchical blocks. Budgeting of a large number of signal paths takes several months and lengthens the total LSI design period.
NEC and NEC Electronics' new design method introduces a "Border Moving Method." After designing hierarchical blocks, the method modifies the boundary of blocks and moves partial signal paths out of the blocks. These partial signal paths, which used to reside inside the blocks, and the partial signal path connecting the blocks are then combined into one signal path. As a result, only the delay for the single signal path has to be considered, eliminating the need for budgeting and re-designing hierarchical blocks. This breakthrough research result has been achieved through the introduction of an intelligent algorithm that minimizes the modification of the boundary, and which has been elaborated enough to allow practical application in the design of real large-scale LSI.
This new method has already been applied to the actual design of several LSIs with satisfactory results. Moreover, the trial proved a substantial performance improvement and a decrease in design time as compared with conventional design methods. NEC and NEC Electronics consider this method to be effective in shortening the design period for large scale and high speed LSIs, and are ready to apply the technology in-house to LSIs for NEC's products such as supercomputers (SX Series), enterprise server products (NX 7700i Series) and platforms, allowing the timely provision of high quality products to customers.
NEC presented the results of this research on the 27th of July at the Design Automation Conference 2006 (DAC 2006), the world's largest international conference on system LSI design (July 23-28, San Francisco, USA).
