Samsung Electronics said Thursday it has begun mass production of three-bit vertical multi-level-cell (MLC) three-dimensional (3D) Vertical NAND (V-NAND) flash memory for use in solid state drives. "With the addition of a whole new line of high density SSDs that is both performance- and value-driven, we believe the 3-bit V-NAND will accelerate the transition of data storage devices from hard disk drives to SSDs," said Jaesoo Han, Senior Vice President, Memory Sales & Marketing, Samsung Electronics.

The 3-bit V-NAND is Samsung’s latest second generation V-NAND device, which utilizes 32 vertically stacked cell layers per NAND memory chip. Each chip provides 128 gigabits (Gb) of memory storage.

In Samsung’s V-NAND chip structure, each cell is electrically connected to a non-conductive layer using charge trap flash (CTF) technology. Each cell array is vertically stacked on top of one another to form multibillion-cell chips.

The use of 3 bit-per-cell, 32-layer vertically stacked cell arrays raises the efficiency of memory production. Compared to Samsung’s 10 nanometer-class 3-bit planar NAND flash, the new 3-bit V-NAND has more than doubled wafer productivity.

Samsung introduced its first generation V-NAND (24 layer cells) in August 2013, and introduced its second generation V-NAND (32-layer) cell array structure in May 2014.

Samsung produced the first SSDs based on 3-bit planar NAND flash in 2012.