TSMC will present papers on its research into emerging memory, two-dimensional materials, and system integration technologies at the 2019 Symposia on VLSI Technology & Circuits, a conference in the field of microelectronics.

The VLSI Symposia, which will be held from June 9-14 in Kyoto, Japan, invited TSMC to deliver a paper on the state of research in embedded Magnetoresistive Random-Access Memory (eMRAM), and further highlighted three TSMC papers for addressing the theme of the 2019 conference, “Pushing the Limits of Semiconductors for a United and Connected World”.

TSMC's paper “Recent Progress and Next Directions for Embedded MRAM Technology” is addressing eMRAM, a nonvolatile memory with potential to replace conventional embedded flash, which is beginning to hit the limits of its scaling. This paper describes results for a 22nm eMRAM that is solder-reflow capable, meaning it is able to endure the high temperatures of soldering in the packaging process without losing data pre-stored in the memory during the wafer manufacturing process. Compared to 28nm embedded flash, it requires fewer additional mask layers, and delivers significant improvement in both write speed and endurance, according to TSMC. This solder-reflow capable eMRAM is optimal for applications where retention of pre-stored data is critical, such as wearables and Internet of Things (IoT) devices. At the same time, the paper also shows that where solder-reflow capability is not required, enhanced eMRAM performance with lower write power consumption and faster read time make it a viable, dense working RAM, which is also nonvolatile. Applications such as low-power consumption machine learning inference processors could benefit from these characteristics.

One of the major challenges to transistor scaling at 3nm and beyond is that the channel allowing electrons to flow through a transistor must not only be shorter, but thinner as well to ensure good switching behavior. This has led to a search for so-called “two-dimensional” channel materials. TSMC’s paper “First Demonstration of 40nm Channel Length Top-Gate WS2 pFET Using Channel Area-Selective CVD Growth Directly on SiOx/Si Substrate” demonstrates the potential for high-volume production using a promising 2D material, tungsten disulphide (WS2). It describes a short-channel transistor with WS2 channel made using the well-established semiconductor manufacturing process of chemical vapor deposition (CVD) directly on a silicon substrate. CVD offers a much simpler method of volume production than the conventional process of making a thin film of WS2, which would require the material to be first deposited on a sapphire substrate, then removed and placed on a silicon wafer. The research shines additional light on the way forward for volume production of future generations of transistors.

TSMC’s other two highlighted papers also address scaling, but at the level of an entire system rather than the individual transistor. Both offer a path to a system made up of “chiplets.” Rather than the “system-on-chip” (SoC) approach combining every component of a system on a single die, chiplets split functions into small separate dies that can be made with different process technologies, offering both flexibility and cost savings. In addition, smaller dies inherently enjoy better yields than large dies. However, to achieve performance comparable to a SoC, chiplets must be able to communicate with each other through dense, high-speed, high-bandwidth connections.

TSMC’s paper “A 7nm 4GHz Arm-core-based CoWoS Chiplet Design for High-Performance Computing” details a dual 7nm chiplet system in TSMC’s Chip on Wafer on Substrate (CoWoS) advanced packaging solution. Each chiplet features an Arm core performing at 4GHz for high-performance computing applications. The paper also validates an on-die mesh bus, also operating at 4GHz, connecting the Arm core in each chiplet to its memory cache. In turn, the two chiplets connect with each other through TSMC’s Low-voltage-In-Package-INterCONnect (LIPINCON), reaching data rates of 8 gigabits per second per pin (Gb/s/pin) with good power efficiency, versus performance ranging from 2 to 5.3 Gb/s/pin for comparable interconnect solutions demonstrated in recent papers.

Finally, TSMC will showcase its 3D integration technology with the paper “3D Multi-chip Integration with System on Integrated Chips (SoIC)”. The SoIC solution enables known good dies of different sizes, process technologies, and materials to be directly stacked together. Compared to typical 3DIC solutions with micro-bumps, TSMC’s SoIC delivers higher bump density and speed, while consuming much less power, the paper found. What’s more, SoIC is a “front-end” integration solution connecting two or more dies before they are packaged. Therefore, a SoIC stack can be further integrated with other SoIC or chips in one of TSMC’s “back-end” advanced packaging technologies such as InFO or CoWoS, offering a powerful “3D-by-3D” system-level solution.

In addition to the highlighted research above, TSMC also contributed to a paper by Qualcomm Inc., “7nm Mobile SoC and 5G Platform Technology and Design Co-Development for PPA and Manufacturability”, reporting on Qualcomm’s Snapdragon SDM855 mobile system-on-chip and world’s first commercial 5G platform using 7nm FinFET technologies.