Xilinx and TSMC Team to Enable High Performance FPGAs on TSMC's 16-nanometer FinFET
Xilinx and TSMC are teaming together to create FPGAs built on TSMC's 16-nanometer FinFET 16FinFET process, a program Xilinx calls 'FinFast.'
The two companies will work together to co-optimize the FinFET process with Xilinx's UltraScale architecture. The program will deliver 16FinFET test chips later in 2013 and first product in 2014.
The companies are also engaged in leveraging TSMC's CoWoS 3D IC manufacturing flow.
TSMC recently announced that it is accelerating the production schedule of its 16FinFET process to 2013.
Xilinx has worked with TSMC to infuse high-end FPGA requirements into the FinFET development process, just as it did in the development of 28HPL and 20SoC processes. To gain optimal results, further co-optimizations will be done across TSMC's process technology and Xilinx's UltraScale architecture and next-generation tools. UltraScale is Xilinx's new ASIC-class architecture, developed to scale from 20-nanometer planar, through 16-nanometer and beyond FinFET technologies, and from monolithic through 3D ICs.
Earlier in 2013, Altera and Intel announced that the pair had entered into an agreement for the future manufacture of Altera FPGAs on Intel's 14nm tri-gate transistor technology.
In related news, TSMC has today certified system-on-chip development and design tools for its 16nm FinFET Process, provided by Cadence and Synopsys.
Both companies' tools have achieved version 0.1 of design rule manual (DRM) and SPICE model tool certification for TSMC?s 16-nanometer FinFET process.
The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology. The certified Cadence tools are Spectre, Liberate, Virtuoso, Encounter Digital Implementation (EDI) System, Encounter Timing System, Virtuoso Power System, Encounter Power System, Physical Verification System and QRC Extraction.
Additionally, TSMC has certified the production-ready Cadence design flow for its 20-nanometer manufacturing process. The full tool chain was certified at 20 nanometers through the design of an ARM Cortex-A9 processor, and is the first integrated tool certification for TSMC 20SoC process technology. The Cadence tools used are Virtuoso, EDI System, Encounter Timing System, Encounter Power System, Virtuoso Power System, Physical Verification System and QRC Extraction.
Cadence and TSMC also recently announced their collaboration on 16 nanometers.
The certified Synopsys IP and services include all the relevant 16-nm technology routing rules, verification runsets, extraction rundecks and Interoperable Process Design Kits (iPDK).
The certified Synopsys Galaxy Implementation Platform features support for TSMC 16-nm V0.1 design rules. TSMC has certified a full suite of Synopsys implementation tools that are FinFET-ready. This includes:
- IC Compiler: Double patterning technology (DPT)-aware placement and routing provides optimal area and performance results that can be reliably decomposed during manufacturing
- IC Validator: DRC and DPT rule compliance check verifying FinFET parameters including fin boundary rules and expanding dummy cells.
- PrimeTime: Accurate delay calculation and timing analysis to include impact of double patterning
- StarRC: Extraction of parasitics impacted by the 3-D structure of FinFET devices and relevant extensions to Interconnect Technology Format (ITF)
- FineSim and CustomSIM: Correct and accurate functionality with the FinFET BSIM-CMG models
- Custom Designer and Laker Layout: Improved productivity through connectivity-assisted editing with support for 16-nm constraints to help manage design-rule complexity
The companies are also engaged in leveraging TSMC's CoWoS 3D IC manufacturing flow.
TSMC recently announced that it is accelerating the production schedule of its 16FinFET process to 2013.
Xilinx has worked with TSMC to infuse high-end FPGA requirements into the FinFET development process, just as it did in the development of 28HPL and 20SoC processes. To gain optimal results, further co-optimizations will be done across TSMC's process technology and Xilinx's UltraScale architecture and next-generation tools. UltraScale is Xilinx's new ASIC-class architecture, developed to scale from 20-nanometer planar, through 16-nanometer and beyond FinFET technologies, and from monolithic through 3D ICs.
Earlier in 2013, Altera and Intel announced that the pair had entered into an agreement for the future manufacture of Altera FPGAs on Intel's 14nm tri-gate transistor technology.
In related news, TSMC has today certified system-on-chip development and design tools for its 16nm FinFET Process, provided by Cadence and Synopsys.
Both companies' tools have achieved version 0.1 of design rule manual (DRM) and SPICE model tool certification for TSMC?s 16-nanometer FinFET process.
The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology. The certified Cadence tools are Spectre, Liberate, Virtuoso, Encounter Digital Implementation (EDI) System, Encounter Timing System, Virtuoso Power System, Encounter Power System, Physical Verification System and QRC Extraction.
Additionally, TSMC has certified the production-ready Cadence design flow for its 20-nanometer manufacturing process. The full tool chain was certified at 20 nanometers through the design of an ARM Cortex-A9 processor, and is the first integrated tool certification for TSMC 20SoC process technology. The Cadence tools used are Virtuoso, EDI System, Encounter Timing System, Encounter Power System, Virtuoso Power System, Physical Verification System and QRC Extraction.
Cadence and TSMC also recently announced their collaboration on 16 nanometers.
The certified Synopsys IP and services include all the relevant 16-nm technology routing rules, verification runsets, extraction rundecks and Interoperable Process Design Kits (iPDK).
The certified Synopsys Galaxy Implementation Platform features support for TSMC 16-nm V0.1 design rules. TSMC has certified a full suite of Synopsys implementation tools that are FinFET-ready. This includes:
- IC Compiler: Double patterning technology (DPT)-aware placement and routing provides optimal area and performance results that can be reliably decomposed during manufacturing
- IC Validator: DRC and DPT rule compliance check verifying FinFET parameters including fin boundary rules and expanding dummy cells.
- PrimeTime: Accurate delay calculation and timing analysis to include impact of double patterning
- StarRC: Extraction of parasitics impacted by the 3-D structure of FinFET devices and relevant extensions to Interconnect Technology Format (ITF)
- FineSim and CustomSIM: Correct and accurate functionality with the FinFET BSIM-CMG models
- Custom Designer and Laker Layout: Improved productivity through connectivity-assisted editing with support for 16-nm constraints to help manage design-rule complexity
