AMD's upcoming Carrizo chip for notebooks and low-power desktops promise to offer significantly performance gains over the prior generation, Kaveri, along with battery life boost. The company will describe at the International Solid-State Circuits Conference in San Francisco.

AMD’s Carrizo APU is made up of an undisclosed number of "Excavator" CPU cores and eight AMD Radeon cores that serve as an integrated graphics chip. It measures 250.04 square mm. AMD said Monday that the Excavator cores execute 5 percent more instructions per clock than Kaveri, consuming 40 percent less power across 23 percent less die area - 3.1 billion transistors in all.

According to Sam Naffziger, an AMD fellow, Carrizo packs 29% more transistors and squeezes double-digit gains in performance and drops in power consumption out of the same 28nm process and die area as its current Kaveri chip.

AMD uses the extra space to pack its previously external south bridge I/O unit into the die, saving system level power. The company claims the chip is also the first x86 to provide hardware-assisted decode of the new High Efficiency Video Codec (H.265).

AMD claims that the new chip will sport power and performance advantages for some mainstream notebooks over its competitor, Intel’s Broadwell made in a 14nm FinFET process that debuted at CES in January. However, Intel still commands a significant lead in CPU performance. In addition, the 12-35W Carrizo family requires a fan making it too hot and power hungry to find sockets in notebooks.

The ISSCC paper will detail many of the chip’s advances packing its core into a smaller area and delivering power consumption savings, according to co-author Sam Naffziger, one of four AMD corporate fellows and the company’s lead engineer on power issues.

AMD puts hopes in the advanced graphics processor cores packed into the Carrizo chips, which gives the company an edge over Intel's offerings. According to the ISSCC paper, AMD applied to Carrizo physical design techniques from its GPU cores. An auto place-and-route methodology and high density libraries helped shrink the chips metal layer count from 13 to 9 tracks, shrinking wires and saving power.

Other advances enable users to access all 8 GPU cores on the design. In its prior 17W Kaveri chip users could only access 6 of 8 graphics units.

The chip also marks first full implementation of the AMD-led Heterogeneous System Architecture spec for letting GPUs and CPUs share coherent memory links.

The paper also describes a power management techniques AMD applied in Carrizo. They include new techniques for mitigating voltage droop and use of 10 on-chip sensors monitoring frequencies across about 500 pathways.