British chip designer ARM is introducing the Cortex-A76AE, the first in a new line of safety-hardened processors for building features such as automated collision avoidance into vehicles.
The new line of AE, or "Automotive Enhanced", application processors lets chipmakers design chips with security features that allow autonomous cars to meet the toughest safety requirements, the company said on Wednesday.
It expects the first cars using the new Cortex-A76AE processor to hit the roads in 2020.
Existing ARM customers working on autonomous driving platforms include Nvidia, NXP, Renesas, Samsung's Harman business, and Siemens Mentor unit, among others.
As the name suggests, the Cortex-A76AE is based on ARM's Cortex-A76 design. It is a superscalar, out-of-order processor that delivers similar levels of performance as the Cortex-A76 across integer, floating point, memory and machine learning, and achieves similar levels of energy efficiency. Where the Cortex-A76AE is different, is through microarchitectural upgrades for functional safety and added application flexibility.
Cortex AE chips are optimized to be built with the most advanced 7-nanometer circuit wiring, ARM said. The company says its new Silicon on Chip (SoC) designs will require as a little as a few dozen watts of energy rather than the kilowatts now needed in chips to power driverless car prototypes.
Customers can also use the same designs to run other, less safety-critical features like infotainment that can be improved via over-the-air software updates.
This "split-lock" design - combining locked features that can't be changed and unlocked features that can - can share portions of the same chip, promising higher performance and less energy use, which is key for electric-battery powered autonomous vehicles. Split-Lock delivers:
- Flexibility not available in previous lock-step CPU implementations
- CPU clusters in an a SoC can be configured either in 'split mode' for high performance, where two (or four) independent CPUs in the cluster that can be used for diverse tasks and applications
- Or 'lock mode' where CPUs are in lock-step, creating one (or two) pairs of locked CPUs in a cluster, for higher safety integrity applications
- The CPU clusters can be configured to operate in a mix of either mode, post Silicon production
The following are the main microarchitectural highlights of Cortex-A76AE for safety:
- Dual Core Lock-Step (DCLS): The Cortex-A76AE is capable of running in Dual Core Lock-Step (DCLS), and hence is able to contribute towards a system's ASIL D hardware diagnostic coverage requirements.
- Memory protection: The Cortex-A76AE comes with memory protection as standard. It supports Single Error Correction, Double Error Detection (SECDED) ECC and Parity protection in the L1 cache, and SECDED ECC protection with the ability to correct in-line, on the L2 and L3 caches.
- RAS features: As part of the Armv8.2 architecture extension, Cortex-A76AE includes RAS features built in. This includes standardized error reporting across the core and the DSU, error injection as a means of testing fault management, and data poisoning as a way of deferring error aborts till point of execution.
- Integrated comparators: The Cortex-A76AE includes comparators, which are integrated into the design. These blocks compare outputs from the logical and redundant processing elements to detect for divergence. They follow the error reporting scheme as defined in the Armv8.2 RAS architecture.
Apart from the hardware features above, the Cortex-A76AE has been developed on an advanced process for the avoidance of systematic faults. This enables it to meet the ASIL D systematic requirements as standard.
Cortex-A76AE has been designed to act as the decision engine in next generation ADAS and Autonomous Vehicle systems. According to ARM, the chip delivers a 30% uplift in performance over its predecessor, the Cortex-A75, and a 60% increase in performance over Cortex-A72. This boost in performance meets the emerging CPU requirements for autonomous driving of more than 250K DMIPS at less than 15 Watts for the compute cluster. This fits well within an SoC power budget of 30 Watts.
Arm takes the entire system into consideration and to complement Cortex-A76AE, Arm introduced new Automotive Enhanced system IP for designing a comprehensive autonomous-class SoC. The new CoreLink GIC-600AE, CoreLink MMU-600AE and CoreLink CMN-600AE provide critical elements such as high-performance interrupt management, extended virtualization and memory management, and connectivity to multiple CPU clusters to scale performance in safe multicore systems. These products have been designed to enable high-performance systems, targeting ASIL-B to ASIL-D safety integrity, and support the Split-Lock and systematic capabilities for functional safety designed into the Cortex-A76AE.
ARM-based chips are used in 85 percent of car entertainment systems and two-thirds of collision detection processor chips.
Intel has been also working on a roadmap to deliver its first generation of chips for fully autonomous cars starting in 2020, based around its acquisition of collision-detection software maker Mobileye a year ago.
Arm's Automotive IP roadmap
The Cortex-A76AE is the first in a roadmap of "Automotive Enhanced" processors. The new roadmap includes "Helios-AE" and "Hercules-AE", all optimized for 7nm.