Intel researchers will present five papers showcasing technology advances and solutions at IEEE’s 64th International Electron Devices Meeting Dec. 3-5 in San Francisco.
IEDM is a global forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics and modeling.
Intel's papers cover a range of subjects, including one on embedded MRAM, as well as an invited paper on 3D NAND, illustrating the breadth and depth of Intel’s process technology work.
Intel will present key features of production-ready Magnetoresistive RAM-based non-volatile memory (NVM) embedded into its 22FFL FinFET technology. Among other applications, MRAM-based e-NVM is a potential solution for IoT, FPGAs and chipsets with on-chip boot data requirements.
Key features of Intel’s MRAM-based e-NVM include:
- 1 transistor-1 resistor cell, 216nm x 225nm
- >200 degrees C 10-year retention capability
- >10^6 write endurance
- The Magnetic Tunnel Junction-based memory is embedded between metal 2 and metal 4 of the 22FFL process
intel says that the retention and endurance capabilities of this technology are shown on 7.2 Mbit arrays and full 300mm wafers.
Intel will also present its 22nm FinFET (22FFL) process technology for RF and mmWave applications. The company will describe that 22FFL supports both RF and mmWave applications with best-in-class ft and fmax of NMOS above 300 GHz and 450 GHz, respectively. Intel claims its approach offers flicker noise improvement over planar technologies and "excellent" gain-power efficiency to enable low-power wireless applications. The paper will also presents design methodologies to exploit advantages of FinFET technology for RF and mmWave applications.
In another paper, Intel will highlight the co-optimization of process technology, standard cell library offerings and block-level tool-flow-methodology on the company's 10nm node to enable "unprecedented" scaling opportunity for products ranging from high performance client/server to low power mobile/IoT segments.
Intel says that its 10nm short height library enables a 2.7x transistor density scaling from the 14nm counterpart. Taller height libraries are optimized to meet performance and reliability requirements of Intel’s client/server products. The company will analyze power-performance-area tradeoffs at both the standard cell and block level on an industry standard Core IP design.
Regarding 3D NAND, Intel will describe how placing all the CMOS support circuitry under the NAND array has been leveraged to maximize the Gb/mm2 areal densities. It will talk about the 4 bits/cell capability, another significant scaling breakthrough that provides 33 percent higher Gb/mm2 areal density compared to 3 bits/cell. The company says that 3D NAND scaling will continue from increasing the number of layers, despite the key process challenges such as memory hole etching, cell formation in the high aspect ratio memory holes, and improved channel conductivity.
Last bit not least, Intel's researchers will discuss their efforts to utilize state-of-the-art manufacturing techniques for quantum computing research. Intel leveraged its expertise in transistor process technology to create a 300mm high-volume fabrication and e-test line for semiconductor spin qubits.