Interesting papers presented so far at the International Solid State Circuits Conference include Toshiba Memory's 96-layer, 1.33Tb 3D NAND chip and Samsung's new neural network accelerator for smartphones.

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology

Toshiba Memory's NAND stores 4-bits-per-cell and achieves bit density of 8.5Gb/mm2, more than 40% better than a 512Gb TLC 3D NAND device also described at the ISSCC Tuesday by Toshiba and its partner Western Digital.

The device features a die size of 158.4mm2. It utilizes a modified source-bias-negative-sense scheme, allowing for deep negative threshold voltage while maintaining a low supply voltage, according to Noboru Shibata, a Toshiba design engineer who presented the paper at ISSCC.

The QLC Toshiba device also makes use of a modified two-step programming method, enabling it to realize a narrow threshold voltage for QLC with an 18% reduction in typical page programming time, according to the paper.

512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology

In another Toshiba-Western Digital paper presented at ISSCC, the authors described a 128-layer 3-bit-per-cell 3D NAND device that achieves 66mm2 die size and 7.8Gb/mm2 bit density.

The 128-layer device is enabled by three key technologies, including a four-plane architecture with circuit-under-array technology to improve performance per bit density, a multi-die peak-power management system to manage power consumption and improve write throughput, and a 4KB-page-read mode to reduce power consumption, according to the paper.

Samsung takled about a new neural network accelerator for smartphones. Seperately, Toshiba detailed one for self-driving cars.

Energy-Efficient Intelligent Vision Sensor for Next Generation Mobile and Autonomous Applications

Samsung said that a 5.5mm2 block in the latest 8nm Exynos chip delivers 1.9 Tera-operations/second using 8-bot precision running at up to 933 MHz. That’s about the rating for the latest Huawei Kirin processor.

However, the block hits performance of 6.937 TOPS when a neural net allows pruning of up to three-quarters of it weights. The chip delivers a range of 4.5 to 11.5 TOPS/W when consuming from 39mW at 0.5V to 1.553W at 0.8V.

The Samsng chip uses pruning and quantization, running 8- and 16-bit operations to optimize for efficiency and network sparsity.

The Samsung design appears in the latest Exynos chip and is expected to be used in at least some new handsets the South Korean giant is announcing as early as this week. To enhance parallelism it uses two cores, each with two data-staging units sharing 512-KByte scratch pads.

20.5TOPS and 217.3GOPS/mm2Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications

Toshiba described an accelerator for advanced driver assistance systems that delivers up to 20 TOPS and 2 TOPS/W, up from 1.9 TOPS and 564 GOPS/W with its 2015 chip.

Two new image processing cores carried most of work in the new version. Each block processes 8 MPixel images and up to 40 frames/second.

The 94.5mm2 chip was made in a 16nm node. It added to the 2015 design four DSPs, believed to be NeuPro cores from Ceva, as well as three new specialty accelerator blocks.

The Toshiba design packs eight Cortex-A53 cores and two Cortex-R4s, compared to four MIPS cores and no R4 equivalents on the latest Mobileye chips. In addition, the Mobileye chips run at 5W in 7nm, making them more power hungry and expensive than the Toshiba SoC, he said.