Philips to Integrate Its Largest Chip in Bangalore
The Bangalore design centre of the US$36.7 billion Royal Philips Electronics would work on the next generation consumer platform chip design and integrate the whole chip -- the biggest ever designed by Philips, it was announced Thursday.
Philips Semiconductors Chief Technology Officer Rene Penning de Vries told reporters here
that the Bangalore centre -- with over 500 people working on the latest technologies in
SoC and embedded software domains -- is fully staffed and the company is embarking on
designs in the latest technologies, mostly 65nm and 90nm.
"The next generation consumer platform chip will enable new applications for our next generation consumer platform such as HD motion based enhancements and 3D TV", he said. "It will be the biggest chip we have ever designed in this company and will consist of multiple MIPS and Trimedia (DSP) processors and various applications specific IP blocks".
Vries said the chip will be designed in the company's highly advanced 65nm process.
"Developing the chip involves collaborative efforts across multiple sites in Europe and the US. Our Bangalore team will be integrating the whole chip. We will also be working with Philips Research in Bangalore and the Netherlands".
He also announced an initiative, which will allow the design centre here to focus on reusable IP.
"Reuse of IP is essential as chip compexities are increasing at a tremendous rate", he said. "Our team here will become responsible for a large part of our reuse porfolio. We are enhancing our IP development and production capabilities here and expanding our work in the areas of connectivity peripherals", Vries said.
"The next generation consumer platform chip will enable new applications for our next generation consumer platform such as HD motion based enhancements and 3D TV", he said. "It will be the biggest chip we have ever designed in this company and will consist of multiple MIPS and Trimedia (DSP) processors and various applications specific IP blocks".
Vries said the chip will be designed in the company's highly advanced 65nm process.
"Developing the chip involves collaborative efforts across multiple sites in Europe and the US. Our Bangalore team will be integrating the whole chip. We will also be working with Philips Research in Bangalore and the Netherlands".
He also announced an initiative, which will allow the design centre here to focus on reusable IP.
"Reuse of IP is essential as chip compexities are increasing at a tremendous rate", he said. "Our team here will become responsible for a large part of our reuse porfolio. We are enhancing our IP development and production capabilities here and expanding our work in the areas of connectivity peripherals", Vries said.
