Technology licensing company Rambus Inc. today showcased a silicon demonstration of a complete XDR memory system running at data rates up to 7.2Gbps with superior power efficiency. This silicon demonstration consists of Elpida's recently-announced 1Gb XDR DRAM device and an XIO memory controller transmitting realistic data patterns. The XIO memory controller is up to 3.5 times more power efficient than a GDDR5 controller, and the total memory system can provide up to two times more bandwidth than GDDR5 at equivalent power. In addition, the XIO memory controller demonstrated bi-modal operation with support for both XDR DRAM as well as next-generation XDR2 DRAM.

"Future graphics and multi-core processors require significantly higher memory performance under extremely challenging power and thermal constraints," said Martin Scott, senior vice president of Research and Technology Development at Rambus. "This technology demonstration highlights the outstanding power efficiency of the XDR and XDR2 memory architectures at performance levels from 3.2 to 7.2Gbps with scalability to well over 10Gbps."

This silicon demonstration, shown at Denali MemCon 2009 in San Jose, is the first implementation supporting the XDR memory architecture roadmap incorporating innovations developed as part of Rambus' Terabyte Bandwidth Initiative. Implemented in the bi-modal XIO memory controller for XDR2 operation, these innovations include:

- Fully Differential Memory Architecture (FDMA) - enhances signal integrity and increases performance through point-to-point differential signaling of clock, data, and command/address (C/A), an industry first;
- FlexLink C/A - reduces pin count and increases scalability; and
- Enhanced FlexPhase - enables the world's highest memory signaling rates while simplifying routing and board design.

In addition, the XDR2 memory architecture includes:

- Micro-threading of the DRAM core - introduced by Rambus in early 2005, increases data transfer efficiency and reduces power consumption; and
- 16X Data Rate - allows for extremely high data rates with the use of a relatively low-speed system clock.

Built on these technologies, an XDR2 memory system can provide memory bandwidths of over 500GB/s to an SoC. A single 4Byte-wide, 9.6Gbps XDR2 DRAM device can deliver up to 38.4GB/s of peak bandwidth, and the XDR2 architecture supports a roadmap to device bandwidths of over 50GB/s.

With these capabilities, the XDR and XDR2 memory architectures are scalable across a broad range of performance appropriate for multi-core computing, graphics, gaming, and consumer electronics. The XDR memory architecture has already been adopted in products including the Sony PLAYSTATION 3 computer entertainment system, DLP projectors, Teradici PC-over-IP computing systems, and Toshiba's Qosmio laptop PCs and HDTV chip sets.

At the same event, Michael Ching, director of Strategic Development at Rambus, will discuss the future of main memory subsystems beyond DDR3 SDRAM, which must attain faster data rates than 1600MHz while maintaining low power, access efficiency and competitive cost. This discussion will also outline some of the key challenges facing future main memory, and the Rambus innovations that can be applied to advance the main memory roadmap.

Fred Ware, Technical Director, will discuss the increasing application demands of mobile consumer platforms and the performance importance of the underlying memory subsystems. This discussion will outline developments of Rambus as part of its Mobile Memory Initiative and how these technologies address the issues of scalability, power efficiency, power state exit latency, clock recovery, signal integrity, and low-cost packaging.