"The performance advancements achieved by our WSP technology can be utilized in many diverse combinations of semiconductor packaging, such as system-in-package solutions that combine logic with memory," said Tae-Gyeong Chung, vice president, Interconnect Technology Development Team, Memory Division, Samsung Electronics.
In today?s MCPs, memory chips are connected by wire bonding, requiring vertical spacing between dies that is tens of microns deep. That wire bonding process also requires horizontal spacing on the package board hundreds of microns wide for the die-connecting wires. By contrast, Samsung?s WSP technology forms laser-cut micron-sized holes that penetrate the silicon vertically to connect the memory circuits directly with a copper (Cu) filling, eliminating the need for gaps of extra space and wires protruding beyond the sides of the dies. These advantages permit Samsung?s WSP to offer a smaller footprint and thinner package.
Inside the new WSP, the TSV is housed within an aluminum (Al) pad to escape the performance-slow-down effect caused by the redistribution layer. Due to the complexity of DRAM stacking, this represented a much more difficult engineering feat than that accomplished with the first WSP, announced last year involving NAND flash dies.
There has been considerable concern that MCPs with high-speed memory chips with speed of 1.6Gb/ps next generation DRAM, would suffer from performance limitations when connected using current technologies. Samsung said that its WSP technology resolved these concerns.
In addition, as the back side of the wafer is ground away to make a thinner stack of multiple dies, the wafer has had a tendency to curve, creating physical distortion in the die. To overcome this additional critical concern in designing low-profile, high-density MCPs containing DRAM circuitry, Samsung?s wafer-thinning technology, announced last year, has been applied to improve the thin-die-cutting process.