Typically, longer battery life requires lower power consumption in both high performance and low performance modes (MP3 decoding, background processing, etc.). As low performance applications require only tens of MHz operation, SRAM temperature remains around RT, where active and leakage power consumptions are comparable. Given this, the key issue is to reduce active and standby power from HT to RT.
Toshiba's new technology applies a BLPC and DCRC. The BLPC predicts power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It minimizes the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits. The DCRC decreases standby power in the retention circuit by periodically activating itself to update the size of the buffer of the retention driver.
Toshiba presented this development at the 2013 IEEE International Solid-State Circuit Conference in San Francisco, CA on February 20.