TSMC, the world's largest chip maker, today announced its 16-nanometer FinFET Plus (16FF+) process is now in risk production. TSMC claims that the enhanced version of its 16FF process operates 40% faster than the company's planar 20-nanometer system-on-chip (20SoC) process, or consumes 50% less power at the same speed. It is targeted at the next generation of high-end mobile, computing, networking, and consumer applications.

TSMC's 16nm process offers an extended scaling of advanced SoC designs and is verified to reach speeds of 2.3GHz with ARM's "big" Cortex-A57 in high-speed applications while consuming as little as 75mW with the "LITTLE" Cortex-A53 in low-power applications. TSMC says it is making excellent progress in yield learning, and has achieved the best technology maturity at the same corresponding stage as compared to all TSMC's previous nodes.

TSMC's 16FF+ design ecosystem supports a wide variety of EDA tools and hundreds of process design kits with more than 100 IPs, all of which have been silicon validated.

The 16FF+ process is on track to pass full reliability qualification later in November, and nearly 60 designs are currently scheduled to tape out by the end of 2015. Due to rapid progress in yield and performance, TSMC anticipates 16FF+ volume ramp will begin around July in 2015.