TSMC has collaborated with Broadcom on enhancing the Chip-on-Wafer-on-Substrate (CoWoS) platform to support the first and largest 2X reticle size interposer.
With an area of approximately 1,700mm2, this next generation CoWoS interposer technology boosts computing power for HPC systems by supporting more SoCs as well as being ready to support TSMC’s next-generation five-nanometer (N5) process technology.
This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC’s previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.
In this TSMC and Broadcom CoWoS platform collaboration, Broadcom defined the complex top-die, interposer and HBM configuration while TSMC developed the manufacturing process to maximize yield and performance and meet the challenges of the 2X reticle size interposer. TSMC developed a unique mask-stitching process enabling expansion beyond full reticle size, to bring this enhancement to volume production.
CoWoS is part of TSMC’s portfolio of Wafer-Level System Integration (WLSI) solutions enabling system-level scaling both complementary to and beyond shrinking transistors. In addition to CoWoS, TSMC’s 3DIC technology platforms, such as Integrated Fan Out (InFO) and System on Integrated Chips (SoIC) enable innovation through chiplet partitioning and systems integration that achieves greater functionality and enhanced system performance.