Cadence Design Systems, Inc. has collaborated with TSMC to deliver their customers DFM expertise and technology in a service model. In an effort to reduce risk and enable the fastest path to Silicon Realization, Cadence DFM Services include model-based simulation of litho-process checks and virtual chemical mechanical polishing for TSMC 40-nanometer technology and below. The goal is to enable design teams to get help in detecting litho or CMP hotspots in order to fix them prior to tapeout. Cadence is the first EDA partner certified by TSMC for DFM services.

"At 40 nanometers and below, it is essential that design teams take DFM issues into account throughout the design process," said Suk Lee, director of Design Infrastructure Marketing at TSMC. "DFM services from Cadence are a key milestone of our long-term collaboration with Cadence to help our common customers to address critical design needs in advanced technologies."

With the increased manufacturing challenges inherent at smaller geometries, DFM checks are an essential part of design flows at 40 nanometers and below. TSMC’s collaboration with Cadence in DFM services is the latest in a continuum of joint efforts by the two companies to address manufacturing challenges for the most cutting-edge designs.