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TSMC Confident That It Will Lead The 10nm Foundry Segment

TSMC Confident That It Will Lead The 10nm Foundry Segment

Enterprise & IT Jan 18,2016 0

Speking during the company's recent investors meeting, TSMC chairman Morris Chang remained confident that the company will lead the 10nm foundry market segment, and even outlined foundry plans for beyond. TSMC expects to start production of 7nm chips in the first half of 2018, said company co-CEO Mark Liu. However, he did not specify whether the node would be ready for volume production or just risk production.

In addition, TSMC has been engaged in R&D for 5nm process technology for one year, said Liu, adding that the node will be ready for launch in the first half of 2020.

TSMC also revealed it will be ready to use extreme ultraviolet (EUV) lithography to make 5nm chips. "We've made significant progress with EUV to prepare for its insertion, likely in 5nm," Liu indicated.

TSMC's next step, however, remains the implementation of 10nm manufacturing. The company expects to qualify the node which will be ready for customer tape-outs in the first quarter of 2016, Liu said.

CC Wei, TSMC's other co-CEO, noted that TSMC's share of the 14/16nm foundry market segment will rise to more than 70% in 2016 from about 40% in 2015. TSMC's 16nm FinFET processes consisting of 16FF (16nm FinFET), 16FF+ (16nm FinFET Plus) and 16FFC (16nm FinFET Compact) will account for more than 20% of the foundry's total wafer revenues in 2016, Wei said.

The new 16nm FFC node, a low-power and low-cost version of TSMC's 16nm FinFET products, will be ready for volume production in the first quarter of 2016.

TSMC is also on track to move its integrated fan-out (InFO) wafer-level packaging technology to volume production in the second quarter of 2016. "We do not expect adoption by a large number of customers. However, we do expect a few very large volume customers," Wei said.

Apple is rumored to be among the first customers adopting the InFO packaging technology for its upcoming A10 chip for the iPhone 7.

TSMC's integrated fan-out wafer-level packaging (InFO WLP) technology is one of many competing 3D IC technologies that promise higher levels of component integration in a single package with better electrical characteristics.

Among those improvements is the possibility for higher-width memory buses that support lower-power operation necessary for mobile devices.

According to TSMC engineers, InFO WLP also allows for better thermal performance as well as superior performance for radio frequency (RF) components such as cellular modems.



Tags: TSMC
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