At this week’s IEEE IEDM conference, nano-electronics research center imec showcased new ways to boost the performance of advanced compound semiconductor logic devices, as the semiconductor industry tries to find solutions that enable 5nm technology nodes and beyond. Imec’s R&D program on advanced logic scaling is targeting the new and mounting challenges for performance, power, cost, and density scaling for future process technologies. One of the directions that imec is following, looks into beyond-Si solutions, such as integrating high-mobility materials into the channels of CMOS devices to increase their performance, and the integration challenges of these materials with silicon. Gate-All-Around Nanowire (GAA NW) FETs have been proven to offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels) achieving high carrier mobility, are interesting concepts to increase device performance. Tunnel FETs, on the other hand, offering a steeper than 60mV/dec subthreshold swing, are a promising option for ultra-low power applications.
At IEDM, imec presented gate-all-around InGaAs Nanowire FETs (Lg=50nm) that performed at an average peak transconductance (gm) of 2200µS/µm with a SSSAT of 110mV/dec. Imec succeeded in increasing the performance by gate stack engineering using a novel gate stack ALD inter-layer (IL) material developed by ASM, and high pressure annealing. The novel IL/HfO2 stack achieved a 2.2 times higher gm for a device with a gate length (Lg) of 50nm, compared to the reference Al2O3/HfO2 stack.
Imec also presented a planar InGaAs homo-junction TFET with 70 percent Indium (In) content. The increase of In content from 53 to 70 percent in a 8nm channel, was found to significantly boost the performance of the device. A record ON-state current (ION) of 4µA/µm (IOFF = 100pA/µm, Vdd = 0.5V and Vd = 0.3V) with a minimum subthreshold swing (SSmin) of 60mV/dec at 300k was obtained for a planar homo-junction TFET device. It was also shown that subthreshold swing and transconductance in TFET devices were more immune to positive bias temperature instability (PBTI) compared to MOSFET devices.
Imec’s research into advanced logic scaling is performed in cooperation with imec’s partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Panasonic, Qualcomm, Samsung, SK Hynix, Sony and TSMC.