Fujitsu's new proprietary procedures have been implemented for estimating more layout-friendly floor plans, as well as for considering wiring routs and timing closure to optimize internal data buses. These steps will help minimize the "white space" in which no transistors are placed, and thus allow more circuits to fit in a chip.
The technology also automatically synthesizes the net list data for physical layout, without the need to manually change the logic design. This brings improved routability and ease of timing closure, resulting in less time required for final layout process, as well as even higher density integration.
Fujitsu says that incorporating the new methods can improve the circuit density by 33%, and reduce the time for final layout process to as short as one month. The company will integrate the method into its new Customized SoC Solutions, and will be available for the development of RTL-handoff SoCs for its customers.
Fujitsu will start accepting orders to develop SoCs using the new methodology in February 2014.