Samsung gave a detailed look at its 7nm platform, which is likely to be the first chipmaking process to use a the EUV lithography, at the VLSI Symposia international conference in Hololulu.

Samsung gave the first detailed look at its long-awaited 7nm process at the VLSI Symposia in Honolulu this week. The talk was especially newsworthy because Samsung is likely to be the first to introduce a new form of lithography, known as EUV because it uses extreme ultra-violet light, that has been in development for some 30 years.

With the essential equipment developed by ASML, the EUV (Extreme Ultraviolet) lithography uses an EUV light of the extremely short wavelength of 13.5 nm. It allows exposure of fine circuit patterns with a half-pitch below 20 nm that cannot be exposed by the conventional optical lithography using an argon fluoride (ArF) excimer laser that produces deep ultra-violet light with a wavelength of 193nm. These scanners also use a technique called immersion lithography to enhance the resolution, but they still can't pattern critical features at the most advanced nodes without complex and costly multi-patterning steps.

But putting EUV into practical use requires a variety of element technologies, including the light source, optics, masks, photoresist, and lithography tools.

The biggest challenge is the technology that generates a powerful EUV beam of the extremely short wavelength of 13.5 nm. This EUV beam can be taken out from high-temperature and high-density plasma. Two methods are used for producing plasma: the Laser-Produced Plasma (LPP) method that produces plasma by condensing a strong laser beam onto a certain material, and the Discharge-Produced Plasma (DPP) method that produces plasma by a pulsed high-current discharge between electrodes in an atmosphere of certain materials. The EUV beam exiting from the plasma is collected by the condensing mirror, passes through a point called the intermediate focus (IF), and illuminates a reflection-type mask after it has been reshaped by the illumination optics. The EUV beam reflected by the mask is exposed by the projection optics to form a pattern on photoresist that is coated on a wafer surface.

The output power of the light source required for high-volume production is 200 W or more. In addition, the EUV light source for high-volume production requires high reliability that allows non-stop operation without maintenance needed.

At VLSI, Samsung said that 7nm process has a 27nm fin pitch and a 54nm gate pitch, which results in the smallest FinFET transistors reported to date. It also has the smallest high-density SRAM cell size at 0.0262 square microns. The overall result is a 40 percent shrink in comparison with its current 10nm process used to manufacture Qualcomm's Snapdragon 845 and Samsung's own Exynos 9810.

The company also said that by using EUV it achieved better pattern fidelity and less variability at these dimensions. The company achieved a 70 percent better pattern fidelity versus current 193nm ArF immersion scanner with multi-patterning, an advantage that could be translated in better manufacturing yields.

In addition, Samsung said that with EUV at 7nm, it can fabricate contacts and some metal layers with a single step rather than using 193nm ArFi with multiple exposures. Samsung has previously said this will reduce mask steps by at least 25 percent and now it is in posiiton to say that its 7nm technology with EUV will revive the "cost-effectiveness of cutting-edge technolgy." But this cost advantage may hinge on a number of factors including the development of a better EUV pellicles to protect masks from contamination, the dose required to avoid random defects, and new inspection tools to find and repair tiny defects.

Samsung produced 256Mb high-density SRAM test chips using the 7nm platform and achieved yields of more than 50% with good operation. The company also produced a 7nm application processor with a quad-core CPU, six-core GPU and SRAM caches that was fully operational. The 7nm EUV technolgy will deliver 20-30 percent higher transistor performance and use 30-50% lower power, according to Samsung.

The South Korean company plans to start risk production of 7nm later this year. This means that full volume production could start sometime during the first half of 2019, so it seems unlikely that 7nm will be ready in time to produce application processors for the Samsung Galaxy S10 next spring.

Rival Taiwan Semiconductor Manufacturing Co Ltd (TSMC), the world's largest contract chipmaker, has chosen to get 7nm to market faster using current lithography tools. Its first 7nm process, CLN7FF, is already in volume production and TSMC says it has more than a dozen customers and expects to tapeout more than 50 designs by the end of the year for a variety of chips including mobile application processors, server CPUs, graphics processors, FPGAs, network processors and AI accelerators. Apple's A12 processor for the next family of iPhones could be also made using the 7nm process, CLN7FF process.

TSMC has compared CLN7FF with its 16nm technology (CLN16FF+) where it promises a 70% shrink, and either a 30% boost in performace or a 60% reduction in power. Next year, TSMC plans to roll out an enhanced 7nm processor (CLN7FF+) using EUV for some steps. That one will provide an additional 20% shrink and use 10% less power.

The chipmaker plans to start mass production using the 5nm manufacturing process late next year or in early 2020, CEO and vice chairman C.C. Wei said yesterday. The company is to spend NT$750 billion (US$24.75 billion) to build a plant in the Southern Taiwan Science Park in Tainan, construction of which started earlier this year, Wei said at a TSMC technology forum in Hsinchu.

The plant's annual production is expected to surpass 1 million 12-inch silicon wafers, he said.

TSMC's total output for this year is forecast to reach 12 million 12-inch equivalent wafers, with products on the 7nm and 10nm processes to double from last year, he said.

GlobalFoundries announced its first 7nm process at IEDM late last year. The foundry is using ArFi with quadruple patterning, which should soon be in risk production and will be in mass production sometime in 2019. This 7LP process will be used to manufacture AMD and IBM processors.

The 7LP process has a fin pitch of 30nm and gate pitch of 56nm, and the SRAM cell size measures 0.0269 square microns. Overall GlobalFoundries promises 40 percent better transistor performance and a 30 percent cost reduction, compared to the GF's current 14nm process.

Intel expects to start production of 10nm mainstream processors sometime in 2019. This 10nm process also uses ArF immersion with self-aligned quadruple patterning. The 10nm process has a fin pitch of 34nm and gate pitch of 54nm, and a SRAM cell size of 0.0312 square microns.