The memory industry has been challenged to increase the capacity of internal volatile memory such as Static Random Access Memory (SRAM), while decreasing the power consumption required for memory cells. The growing amount of power consumed by leakage current in the memory in a major concern, driving anticipation of a change from the volatile memory now used to a non-volatile memory solution. Toshiba has worked toward this in its continuing development of "Magnetic Tunneling Junction" (MTJ) which operates a high speed and lower power.
Previously, Toshiba integrated 31nm MTJ into 65nm generation transistor circuits, and demonstrated the smallest power consumption for a 4Mb-RAM cache memory. However, in order for this technology to be applied to the cutting edge transistors in the 2X nm and later generations, it is necessary to secure high-speed operation and low-power-consumption operation of the MTJ by using elements miniaturized down to 1X nm.
Toshiba developed 1X nm size MTJ elements by using a new, finer process technology and demonstrated for the first time high-speed operation below 3ns with low current consumption of under 100uA. The company also confirmed that the technology has the data retention demanded of cache memory and exhibited excellent error rate characteristics, with 2–4ns write operations, as required by high-performance cache memory. Testing of repeated performance of 3 ns write operations that assumed typical cache memory operation exhibited error-free write rates. It is expected that the power consumption of computing devices will be reduced even further by reducing the power consumption of the cache memory.
The magnetic memory technology that Toshiba has developed is the result of research conducted by the normally-off computing project funded by NEDO (New Energy and Industrial Technology Development Organization). Toshiba intends to further improve the performance of the new magnetic memory technology, and to continue development of memory compatible with even smaller transistors.