Samsung Announces First 40-nanometer 32 Gb NAND Flash
Samsung today announced major component technology advancements including the 40-nanometer (nm) 32-Gigabit (Gb) NAND flash and the first prototype of the next-generation of memory - PRAM (Phase change Random Access Memory).
The new 32 Gigabit (Gb) NAND flash device is the first memory to incorporate a Charge Trap Flash (CTF) architecture, a new approach to further increase manufacturing efficiency.
The new CTF-based NAND flash memory increases the reliability of the memory by sharply reducing inter-cell noise levels. Its simple structure also enables higher scalability which will eventually improve manufacturing process technology from 40 nm to 30 and even 20nm.
In each 32Gb device, the control gate in the CTF is only 20 percent as large as a conventional control gate in a typical floating gate structure. With CTF, there is no floating gate. Instead, the data is temporarily placed in a ?holding chamber? of the non-conductive layer of the flash memory composed of silicon nitride (SiN). This results in a higher level of reliability and better control of the storage current.
The 32Gb NAND flash memory can be used in memory cards with densities of up to 64-Gigabytes (GBs). One 64GB card can store over 64 hours of DVD resolution movies (40 movies) or 16,000 MP3 music files (1,340 hours).
The CTF design is enabled through the use of a TANOS structure comprised of tantalum (metal), aluminum oxide (high k material), nitride, oxide and silicon. The use of a TANOS structure marks the first application of a metal layer coupled with a high k material to the NAND device.
The TANOS CTF architecture, which serves as the foundation of the 40nm 32Gb CTF NAND flash announced today, was developed after research of the Samsung Semiconductor R&D department. Samsung first revealed the TANOS structure through a paper at the 2003 International Electron Devices Meeting (IEDM). The new 32Gb CTF memory was announced at the sixth annual Samsung press conference in Seoul.
Introduction of a 40nm manufacturing process for 32Gb NAND flash marks the seventh generation of NAND flash that follows the New Memory Growth Theory of double-density growth every 12 months, which was first presented by Dr. Chang Gyu Hwang, president and CEO of Samsung Electronics? Semiconductor Business in a keynote address at ISSCC 2002.
Next Generation of Nonvolatile Memory - PRAM
Samsung also announced that it has completed the first working prototype of what is expected to be the main memory device to replace high density NOR flash within the next decade ? a Phase-change Random Access Memory (PRAM). The company unveiled the 512M-Megabit (Mb) device at its sixth annual press conference in Seoul today.
More scalable than any other memory architecture being researched, PRAM features the fast processing speed of RAM for its operating functions combined with the non-volatile features of flash memory for storage.
A key advantage in PRAM is its extremely fast performance. Because PRAM can rewrite data without having to first erase data previously accumulated, it is effectively 30-times faster than conventional flash memory. PRAM is also expected to have at least 10-times the life span of flash memory.
PRAM will be a highly competitive choice over NOR flash, available beginning sometime in 2008. Samsung designed the cell size of its PRAM to be only half the size of NOR flash. Moreover, it requires 20 percent fewer process steps to produce than those used in the manufacturing of NOR flash memory.
Samsung's new PRAM was developed by adopting the use of vertical diodes with the three-dimensional transistor structure that it now uses to produce DRAM. The new PRAM has the smallest 0.0467um 2 cell size of any working memory that is free of inter-cell noise, allowing virtually unlimited scalability.
Adoption of PRAM is expected to be especially popular in the future designs of multi-function handsets and for other mobile applications, where faster speeds translate into immediately noticeable boosts in performance . High-density versions will be produced first, starting with 512 Mb.
The new CTF-based NAND flash memory increases the reliability of the memory by sharply reducing inter-cell noise levels. Its simple structure also enables higher scalability which will eventually improve manufacturing process technology from 40 nm to 30 and even 20nm.
In each 32Gb device, the control gate in the CTF is only 20 percent as large as a conventional control gate in a typical floating gate structure. With CTF, there is no floating gate. Instead, the data is temporarily placed in a ?holding chamber? of the non-conductive layer of the flash memory composed of silicon nitride (SiN). This results in a higher level of reliability and better control of the storage current.
The 32Gb NAND flash memory can be used in memory cards with densities of up to 64-Gigabytes (GBs). One 64GB card can store over 64 hours of DVD resolution movies (40 movies) or 16,000 MP3 music files (1,340 hours).
The CTF design is enabled through the use of a TANOS structure comprised of tantalum (metal), aluminum oxide (high k material), nitride, oxide and silicon. The use of a TANOS structure marks the first application of a metal layer coupled with a high k material to the NAND device.
The TANOS CTF architecture, which serves as the foundation of the 40nm 32Gb CTF NAND flash announced today, was developed after research of the Samsung Semiconductor R&D department. Samsung first revealed the TANOS structure through a paper at the 2003 International Electron Devices Meeting (IEDM). The new 32Gb CTF memory was announced at the sixth annual Samsung press conference in Seoul.
Introduction of a 40nm manufacturing process for 32Gb NAND flash marks the seventh generation of NAND flash that follows the New Memory Growth Theory of double-density growth every 12 months, which was first presented by Dr. Chang Gyu Hwang, president and CEO of Samsung Electronics? Semiconductor Business in a keynote address at ISSCC 2002.
Next Generation of Nonvolatile Memory - PRAM
Samsung also announced that it has completed the first working prototype of what is expected to be the main memory device to replace high density NOR flash within the next decade ? a Phase-change Random Access Memory (PRAM). The company unveiled the 512M-Megabit (Mb) device at its sixth annual press conference in Seoul today.
More scalable than any other memory architecture being researched, PRAM features the fast processing speed of RAM for its operating functions combined with the non-volatile features of flash memory for storage.
A key advantage in PRAM is its extremely fast performance. Because PRAM can rewrite data without having to first erase data previously accumulated, it is effectively 30-times faster than conventional flash memory. PRAM is also expected to have at least 10-times the life span of flash memory.
PRAM will be a highly competitive choice over NOR flash, available beginning sometime in 2008. Samsung designed the cell size of its PRAM to be only half the size of NOR flash. Moreover, it requires 20 percent fewer process steps to produce than those used in the manufacturing of NOR flash memory.
Samsung's new PRAM was developed by adopting the use of vertical diodes with the three-dimensional transistor structure that it now uses to produce DRAM. The new PRAM has the smallest 0.0467um 2 cell size of any working memory that is free of inter-cell noise, allowing virtually unlimited scalability.
Adoption of PRAM is expected to be especially popular in the future designs of multi-function handsets and for other mobile applications, where faster speeds translate into immediately noticeable boosts in performance . High-density versions will be produced first, starting with 512 Mb.
