Cadence Design Systems, Inc.'s digital and signoff full flow and custom/analog tools have achieved certification on TSMC’s N6 and N5/N5P process technologies.

The Cadence tools have attained the latest N6 and N5/N5P Design Rule Manual (DRM) and SPICE certification, advancing next-generation mobile application development. Cadence and TSMC are working with customers on N6 design starts both on production designs and test chips. Additionally, Cadence and TSMC have active N5/N5P customer engagements underway.

Cadence’s integrated flow ensures that all the tools will work together, and the company is offering the corresponding N6 and N5/N5P process design kits (PDKs) for download.

Cadence delivered a fully integrated digital implementation and signoff tool flow, which has been certified on both TSMC’s N6 and N5/N5P process technologies. The Cadence full flow includes the Innovus Implementation System, Liberate Characterization, Liberate Variety Statistical Characterization, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus Verification System. Additionally, the Genus Synthesis Solution is enabled for these process technologies.

The Cadence digital and signoff tools provide EUV support across the flow. Some of the latest Cadence tool enhancements include expanded EUV layer support and back end of line (BEOL) layer modeling and middle end of line (MEOL) features.

The Cadence custom/analog tools certified on TSMC’s N6 and N5/N5P process technologies include the Spectre Accelerated Parallel Simulator (APS), Spectre X, Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option, Spectre Circuit Simulator, and Voltus-Fi Custom Power Integrity Solution, as well as the Virtuoso custom IC design platform, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso ADE Product Suite.

Universal polygrid snapping and color engine support features have been enabled in N6. Additionally, expanded design rule constraint support with area-based rule, asymmetric coloring rule, voltage-dependent rule (VDR) and analog cell support, including guardring and dummy insertion are enabled for N5/N5P.

TSMC's current processes:

• N7 is the 7nm process in full volume production without EUV.
• N7+ is the second-generation 7nm process using some EUV layers, also in full volume production.
• N6 is a shrink of N7+ giving more performance and an 18% logic density gain.
• N5 is the 5nm process currently in risk production.
• N5P is the performance-enhanced 5nm process.