The L2-L4 cache memories used in the latest processors consume most of the power of the chip.
Generally, there is a trade-off between operation speed and leak power. An SRAM (6T-2MTJ)-type circuit structure offers a fast speed but leaves the path of leak current. On the other hand, a DRAM (1T-1MTJ)-type circuit structure eliminates the leak path but slows the operation speed.
In addition, cashe requires the formation of an Mbit-class array, but that means that the number of errors would be also increased due to process variation.
Toshiba developed circuit technologies to solve the challenges faced when researchers were previously trying to replace SRAM with STT-RAM.
For the first challenge, Toshiba introduced a dual-cell (2T-2MTJ)-type circuit using two MTJs that have complementary resistive states. This structure eliminates the leak path and increases the readout signal intensity because the signals of the two MTJs are read out, improving access speed. Toshiba says that the read time is improved to 4.1ns, which is close to that of SRAM. And the write time is 2.1ns, which is equivalent to that of SRAM.
For the second challenge, Toshiba employed a smart error detection technique that reduces the error rate by more than 90%, matching the an error rate equivalent to SRAM's.
The method reads out data in a normal mode first and switches to the "Salvage mode" when an error is detected. In the normal mode, data is read out from two MTJs constituting a memory cell at the same time. In the Salvage mode, data is read out from one MTJ at a time. As a result, it became possible to specify a bit that caused an error and correct it.