Cadence Design Systems, Inc. today unveiled the first silicon-proven, long-reach 112G SerDes IP in 7nm running at 112 Gbps. The device allows for the creation of high-port density networking products for cloud-scale and telco datacenters.
SerDes stands for serializer-deserializer. They are really two separate devices, the transmitter (serializer) and receiver (deserializer), although they are usually used in pairs to provide bidirectional communication.
SerDes has become so important in semiconductor design. Provided that the chips have got bigger and more complex, and buses got wider, the number of pins required started to get out of control. The solution was to switch from parallel interfaces with a pin for each bit to serial interfaces running at very high data rates. This got the number of pins under control at the cost of additional complexity in the SerDes on each chip, and more complex board and package design, and especially signal integrity analysis.
In addition, today's huge datacenters require networking of various forms, from the servers to the top of the rack router, from rack to rack, and long-haul out of the datacenter across the country or the world. Again one of the limiting resources is space for the "pins", in this case the space on the front panel where the copper or fiber optic cables connect.
Early adopters in the high-end cloud datacenter market are now installing 400G Ethernet ports, with 400G Ethernet expected to go mainstream in 2020 as early adopters begin 800G Ethernet deployment.
The company claims that 7nm 112G PAM-4 SerDes IP delivers industry-leading power, performance and area (PPA) efficiency. The technology doubles the data rate of 56G SerDes, meeting the high-speed connectivity needs for emerging data-intensive applications such as machine learning and neural networks.
Cadence says its 112G serdes test chip is a working working, as you see on the picture below and the real eye-diagram.
The 112G serdes is base don on technology gained from Cadence's 2017 acquisition of nusemi inc. Key benefits include:
- Firmware-controlled adaptive power design provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements
- DSP-based architecture provides data recovery for lossy and noisy channels
- Extended reach capability enables the use of lower cost PCBs
- Multi-rate support, including 112/56Gbps PAM-4 (four-level pulse amplitude modulation) and 56/28/10Gbps NRZ (non-return-to-zero) data rate, provides backward compatibility with legacy equipment operating at lower speeds
- 7nm silicon,
- PPA optimized for 112G LR and MR
- >35dB insertion loss
- Firmware controlled adaptive power optimization
- Supports entire Ethernet range 10G/25G/50G/100G
- 112/56G PAM-4 and 56G/25G/10G NRZ
- RX FFE + DFE and TX FIR
- Support for N-S and E-W placement
- Fully autonomous startup and adaptation without requiring ASIC intervention
- Integrated BIST capable of producing and checking PRBS (pseudo-random binary sequence)