Fujitsu Develops Chip-Simulation Environment for Mobile Phones
Fujitsu developed a simulation environment for modeling logic system-on-chips (SoCs) used in mobile phones, that will enable high-precision assessment of system performance by using software that runs on the Symbian OS.
By applying this assessment environment during upstream design - early design stages - of a new handset model to evaluate the system's overall performance, and by feeding this information back into the chip design process, the risk of the need for re-design can be avoided, thereby enabling an earlier start of the software development phase and resulting in lower overall development costs.
For mobile phones and other consumer electronics for which both hardware and software are rapidly advancing and expanding, there is a growing need to be able to comprehensively and quantitatively estimate system performance at an early stage in the design process. For example, when designing a graphic user interface (GUI) - which requires responsiveness that enables user-friendly ease of operation - it can be difficult to estimate system performance of actual products by employing only simple estimation methods, for such complicated multi-functional systems. If the difference between the estimate and the actual product is significant, re-design or limitation of the product's features become necessary, thus potentially leading to lost business opportunities.
Typically, in order to estimate real-world performance of a new handset model, an environment that simulates chip operation was developed. Developing a model generally requires implementation of design data. However, deciding the plan for the implementation design requires an assessment based on the model, resulting in a contradictory situation in which the implementation design and the model are each based on the other. Also, in order to develop new functions, two different methods needed to be employed: one for model development and one for implementation and development.
In order to obtain a reliable performance estimate, a model featuring highly accurate processing time simulations is required. At the same time, to find the best design plan, a model that can handle high-speed processing of iterations - for numerous combinations of components and settings - within a short time is essential. However, due to the fact that there is almost nearly always a tradeoff between speed and accuracy, it is difficult to simultaneously achieve both.
Fujitsu Laboratories developed two new technologies, both based on electronic system level (ESL) technology, to address these challenges.
General-purpose components for which operations can be modified on demand were developed. By editing a program region that describes the operating patterns of the component, the user can control how that component will behave when embedded in the model. As the runtime status can even be modified by the model during an assessment, components for which operation is tied to software can be seamlessly assessed within the same model.
For example, for a component that processes image data while linked to software, for a given volume of data to process, system performance will be affected by factors such as the following: processing units that divide the data, the interval at which they are transmitted, and where they are inserted into the system bus. By embedding one of these newly-developed general-purpose components in place of the component to be assessed, the data-dividing increments and intervals can be modified, making it easy to assess how performance is affected by these changes.
To determine the accuracy of each component that goes into a model, one needs to be able to estimate the effect that each component's accuracy exerts on system performance. A mechanism was developed that enables easy combination or mixing of components of different accuracy levels. This makes it possible to segregate functional units from interface units and build a model in the absolute least number of steps.
By combining speed-priority components - that have minimal impact on system performance even when required accuracy is lowered - with accuracy-priority components which feature significant impact on system performance, it is now possible to build a model that features both speed and accuracy.
Based on this technology, Fujitsu Laboratories modeled a mobile phone system-on-chip (SoC) that was in the actual design stage, developed an environment that uses the world's first assessment software on Symbian OS, and fed the results of the analysis back into the design process. This demonstrated the feasibility of overall system assessments without having to wait for actual implementation, a reduction of approximately one year compared to if a system-assessment process using actual equipment were used. This model maintained the required degree of accuracy in the performance assessment, with operational speed performance that is several thousand times faster than previous models (Fujitsu comparison). For example, performance assessment for 1 second, that previously would have required several days, can be reduced to several dozen minutes.
Thus, model-based assessments can be reiterated within a short period, enabling estimation of system-level performance even during upstream design. This makes it possible to optimize design plans without the need to wait for actual chip development to be completed, thereby reducing the risk of having to go back and re-design. In addition, the software development phase can be started sooner.
For mobile phones and other consumer electronics for which both hardware and software are rapidly advancing and expanding, there is a growing need to be able to comprehensively and quantitatively estimate system performance at an early stage in the design process. For example, when designing a graphic user interface (GUI) - which requires responsiveness that enables user-friendly ease of operation - it can be difficult to estimate system performance of actual products by employing only simple estimation methods, for such complicated multi-functional systems. If the difference between the estimate and the actual product is significant, re-design or limitation of the product's features become necessary, thus potentially leading to lost business opportunities.
Typically, in order to estimate real-world performance of a new handset model, an environment that simulates chip operation was developed. Developing a model generally requires implementation of design data. However, deciding the plan for the implementation design requires an assessment based on the model, resulting in a contradictory situation in which the implementation design and the model are each based on the other. Also, in order to develop new functions, two different methods needed to be employed: one for model development and one for implementation and development.
In order to obtain a reliable performance estimate, a model featuring highly accurate processing time simulations is required. At the same time, to find the best design plan, a model that can handle high-speed processing of iterations - for numerous combinations of components and settings - within a short time is essential. However, due to the fact that there is almost nearly always a tradeoff between speed and accuracy, it is difficult to simultaneously achieve both.
Fujitsu Laboratories developed two new technologies, both based on electronic system level (ESL) technology, to address these challenges.
General-purpose components for which operations can be modified on demand were developed. By editing a program region that describes the operating patterns of the component, the user can control how that component will behave when embedded in the model. As the runtime status can even be modified by the model during an assessment, components for which operation is tied to software can be seamlessly assessed within the same model.
For example, for a component that processes image data while linked to software, for a given volume of data to process, system performance will be affected by factors such as the following: processing units that divide the data, the interval at which they are transmitted, and where they are inserted into the system bus. By embedding one of these newly-developed general-purpose components in place of the component to be assessed, the data-dividing increments and intervals can be modified, making it easy to assess how performance is affected by these changes.
To determine the accuracy of each component that goes into a model, one needs to be able to estimate the effect that each component's accuracy exerts on system performance. A mechanism was developed that enables easy combination or mixing of components of different accuracy levels. This makes it possible to segregate functional units from interface units and build a model in the absolute least number of steps.
By combining speed-priority components - that have minimal impact on system performance even when required accuracy is lowered - with accuracy-priority components which feature significant impact on system performance, it is now possible to build a model that features both speed and accuracy.
Based on this technology, Fujitsu Laboratories modeled a mobile phone system-on-chip (SoC) that was in the actual design stage, developed an environment that uses the world's first assessment software on Symbian OS, and fed the results of the analysis back into the design process. This demonstrated the feasibility of overall system assessments without having to wait for actual implementation, a reduction of approximately one year compared to if a system-assessment process using actual equipment were used. This model maintained the required degree of accuracy in the performance assessment, with operational speed performance that is several thousand times faster than previous models (Fujitsu comparison). For example, performance assessment for 1 second, that previously would have required several days, can be reduced to several dozen minutes.
Thus, model-based assessments can be reiterated within a short period, enabling estimation of system-level performance even during upstream design. This makes it possible to optimize design plans without the need to wait for actual chip development to be completed, thereby reducing the risk of having to go back and re-design. In addition, the software development phase can be started sooner.
